LEON3 Processor

The LEON3 is a synthesisable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture. The model is highly configurable and particularly suitable for system-on-a-chip (SOC) designs.

LEON3 supports both asymmetric and symmetric multiprocessing (AMP/SMP). Up to 16 CPUs can be used in a multiprocessing configuration.

LEON3 is also available in a fault-tolerant version, the LEON3FT. You can find more information here.



The LEON3 integer unit implements the full SPARC V8 manual, including hardware multiply and divide instructions. The number of register windows is configurable within the limit of the SPARC manual (2 - 32), with a default setting of 8. The pipeline consists of 7 stages with a separate instruction and data cache interface (Harvard architecture).

LEON3 has a highly configurable cache system, consisting of a separate instruction and data cache.
Both caches can be configured with 1 - 4 ways, 1 - 256 KiB/way, 16 or 32 bytes per line. The instruction cache maintains one valid bit per 32-bit word and uses streaming during line-refill to minimize refill latency. The data cache has one valid bit per cache line, uses write-through policy and implements a double-word write-buffer. Bus-snooping on the AHB bus can be used to maintain cache coherency for the data cache. Local scratch pad ram can be added to either of the instruction and data caches to allow 0-waitstates access instruction or data memory without any AHB bus access.

The LEON3 integer unit provides interfaces for a floating-point unit (FPU), and a custom co-processor.
Two FPU controllers are available, one for the high-performance GRFPU and one for the GRFPU-Lite core. The floating-point processors and co-processor execute in parallel with the integer unit, and does not block the operation unless a data or resource dependency exists.


Quick links

- (LINKS will be fixed when the webpage goes online)

- Documentation

- Detailed feature set

- Software Ecosystem Overview

- Download open-source code (GPL license)

- Excel sheet for SOC area estimation

- DISCOURSE community (for open-source users)

- LEON-RTG4 example bitstreams

- GR716 - Rad-Hard LEON3FT Microcontroller

- GR712RC - Dual-core LEON3FT Processor



Availability and licensing

LEON3 is part of the GRLIB IP library. The open-source version of the library is distributed under the GNU GPL license and can be downloaded here.

The LEON3  can also be obtained under commercial licensing conditions, enabling proprietary designs and taking advantage of a support agreement. Please see the GRLIB IP Core User's Manual - Processor license overview for the license types.

Contact us if you want to use LEON3 in a commercial product.



The LEON3 processor can be synthesised with common synthesis tools from vendors such as Synopsys, Mentor, Xilinx, Microsemi, Lattice and NanoXplore.

The GRLIB IP library contains LEON3 template designs for several popular FPGA prototyping boards. Pre-synthesized FPGA programming files are also provided, see LEON-RTG4.


Software Ecosystem

Being SPARC V8 conformant, compilers and kernels for SPARC V8 can be used with LEON3 (kernels will need a LEON BSP). To simplify software development, We provide several toolchains and operating systems.

Check the software overview webpage for all the details.

Debugging is generally done using the GDB debugger, and a graphical front-end such as DDD or Eclipse. The GRMON monitor interfaces to the LEON5 on-chip debug support unit (DSU), implementing a large range of debug functions as well as a GDB gateway.

The LEON3 processor is also supported by our TSIM3 and GRSIM simulators.

SPARC Conformance

LEON3 has been certified by SPARC International as being SPARC V8 conformant. The certification was completed on May 1, 2005.


Detailed Feature set

 The LEON3 processor has the following features:

  • SPARC V8 instruction set with V8e extensions
  • Advanced 7-stage pipeline
  • Hardware multiply, divide and MAC units
  • Hardware floating-point support
  • Separate instruction and data cache (Harvard architecture) with snooping
  • Configurable caches: 1 - 4 ways, 1 - 256 kbytes/way. Random, LRR or LRU replacement
  • Local instruction and data scratchpad RAM, 1 - 512 Kbytes
  • AMBA 2.0 AHB bus interface
  • High Performance: 1.4 DMIPS/MHz, 1.8 CoreMark/MHz (gcc -4.1.2)
  • Advanced on-chip debug support with instruction and data trace buffer
  • SPARC Reference MMU (SRMMU) with configurable TLB
  • Symmetric Multi-processor support (SMP)
  • Power-down mode and clock gating
  • Robust and fully synchronous single-edge clock design
  • Up to 125 MHz in FPGA and 400 MHz on 0.13 um ASIC technologies
  • Fault-tolerant and SEU-proof version available for space applications
  • Extensively configurable
  • Large range of software tools: compilers, kernels, simulators and debug monitors


The LEON3 processor is fully parametrizable through the use of VHDL generics and does not rely on any global configuration package. It is thus possible to instantiate several processor cores in the same design with different configurations. The LEON3 template designs can be configured using a graphical tool built. This allows new users to quickly define a suitable custom configuration. The configuration tool not only configures the processor, but also other on-chip peripherals such as memory controllers and network interfaces.


Probabilistic platform

The LEON3 processor was extended within the PROXIMA project to build a platform with hardware support that enables probabilistic timing analysis. These extensions, including extensions for GRLIB's Level-2 cache, can also be obtained from us.




Item File
LEON3 IP core documentation

GRLIB IP Core User's Manual,  see LEON3

LEON3 Product Brief

leon3 Product Brief.pdf