TSIM3-GR765

TSIM3-GR765 is an instruction-level simulator capable of emulating the GR765 octa-core microprocessor in RISC-V NOEL-V and SPARC LEON5 mode. The simulator includes features such as non-intrusive debugging, profiling, tracing and instruction level code coverage.

GR716B-MIDI

Compact evaluation platform for the GR716B mixed-signal rad hard microcontroller and the CertusPro-NX FPGA.

GRMON4

The most recent version of our GRMON debug tool provides complete control over SPARC LEON and RISC-V NOEL processors with enhanced features like advanced breakpoints, GUI, and support for JTAG, Ethernet, and SpaceWire debug connections.

LEON/NOEL C/C++ IDE

We provide a quick-start guide on how to set up the Eclipse framework or Microsoft Visual Code to be used for the development of LEON/NOEL-V applications, together with a GCC tool-chain.

TSIM2

TSIM2 is an instruction-level simulator capable of emulating ERC32- and LEON2/3/4-based single-processor systems, such as GR712RC (one processor emulated), UT699, UT699E, UT700, AT697 and AT7913E (Spw-RTC).

TSIM3

Instruction-level simulator capable of emulating single- and multi-core processor systems based on the LEON2/3/4 processors with high simulation accuracy. It is highly user-extensible, includes functionalities such as a scriptable Tcl frontend, GDB support, and using TSIM as a library. TSIM3 also includes features such as non-intrusive debugging, profiling, tracing and instruction level code coverage.

GRMON2

An older version of our debug monitor. It offers robust control and debugging capabilities for LEON cores and various interface options.

GRMON3

The previous version of our GRMON debug tool. It provides complete control over LEON and NOEL cores with enhanced features like advanced breakpoints, GUI, and multi-interface support including JTAG, Ethernet, and USB.

TM/TC EGSE

The EGSE is ideally suited for the verification of FPGA designs and validation of ASIC devices, as well as during the integration of complete TM/TC boards or communication subsystems.

GRESB SpaceWire/Ethernet Bridge

The GRESB is a SpaceWire/Ethernet Bridge with routing capabilities that facilitates rapid development and testing of equipment with SpaceWire interfaces.

GR-CPCI-XC7K

AMD/Xilinx Kintex-7 FPGA development board in compact PCI, 6U, 2 slots format.

GR-VPX-XCKU060

OpenVPX compatible, 6U format, Payload profile development board with an AMD Kintex Ultrascale 060 FPGA.

GR-CPCIS-XCKU

AMD/Xilinx Kintex Ultrascale FPGA development board. Designed in 6U CPCI-S format.

GR718B-BOARD

Development board for the GR718B Radiation-Tolerant 18x SpaceWire router, designed in 6U Compact PCI format.

GR-CPCI-GR716-DEV

Interface board in 6U CPCI format, to be used with the GR716-BOARD. Provides access to all interfaces and additional extension options.

GR716-BOARD

Evaluation Board intended for rapid evaluation of the GR716 rad hard microcontrollers.

GR716-MINI

Very compact (50mm x 35mm) evaluation platform for the GR716 mixed-signal rad hard microcontrollers.

GR712RC-BOARD

Development board for the GR712RC dual-core fault-tolerant LEON3FT SPARC V8 processor. Designed in a Double Eurocard format.

GR740-MINI

Compact evaluation platform designed to showcase the capabilities of the GR740 SoC and the CertusPro-NX FPGA.

GR-VPX-GR740

Development board for the GR740 quad-core 32-bit fault-tolerant LEON4FT SPARC V8 processor. Designed in 6U OpenVPX format.

GR-CPCI-GR740

Development board for the GR740 quad-core fault-tolerant LEON4FT SPARC V8 processor. Designed in 6U Compact PCI format.

PPS Timer

GRPPSTIMER is a PPS timer IP core providing basic timekeeping functions such as an Elapsed Time counter, according to the CCSDS Unsegmented code specification. It also comprises a frequency synthesizer and can be synchronized using a Pulse Per Second (PPS) input signal.

Hardware Security Module

Hardware security module IP core with function to support crypto key storage, boot authentication, supervision, and offloading of cryptographic functions.

Elliptic Curve Cryptography

The GRECC core implements encryption and decryption for an elliptic curve based on 233-bit key and point lengths. The implemented curve is denoted as sect233r1 or B-233.

AES 128

The GRAES core implements the AES-128 symmetric encryption algorithm for high-throughput applications.

NOEL3

The NOEL3 is a configurable RISC-V processor IP core, described in VHDL. The architecture is designed to utilize a small area footprint and to maintain execution predictability.

Reed-Solomon

The Reed-Solomon IP cores provide an alternative to traditional Hamming codecs for memory protection - EDAC - functionality. The IP cores are especially useful in SDRAM and DDR memory controllers for space applications.

DMA Controller with Crypto

GRDMAC2 is a flexible direct memory access controller with AHB or AXI4 interface. It can be configured to include hardware accelerators for AES-256 and SHA-256 functionalities.

AHB to AXI Bridges

APB Controller

AHB Controller

L2 Cache

The L2C is a Level-2 cache IP core for processors with AHB interfaces. It is configurable to enable EDAC protection for the data and tag memory.

Fault Tolerant On-chip SRAM

IEEE-754 Floating Point Unit

The GRFPU is an IEEE-754 compliant floating-point unit, supporting both single and double precision operands. The advanced design combines high throughput with low latency.

DDR266

The DDRSPA can interface two 16,32 or 64-bit wide DDR266 banks. Both memory and configuration register accesses are performed through an AHB slave interface. The core also supports mobile DDR (LPDDR).

DDR2

The DDR2SPA can interface two 16,32 or 64-bit wide DDR2 banks. Both memory and configuration register accesses are performed through an AHB slave interface.‍

PC133 SDRAM

The FTSDCTRL interfaces PC133 SDRAM-compatible devices. Supported bus widths are 32-/39- and 64-bit. EDAC is only supported for 39-bit buses.

Combined PROM/IO/SRAM

The FTSRCTRL uses a common 32-bit memory bus to interface 32-bit PROM, IO and SRAM devices. 8-bit PROM devices are also supported. It also provides EDAC correcting one and detecting two errors for the PROM and SRAM areas using a (39, 7) BCH code.

Combined PROM/IO/SRAM/SDRAM

The FTMCTRL can handle four types of devices: PROM, asynchronous static ram (SRAM), synchronous dynamic ram (SDRAM) and memory mapped I/O devices (I/O). The PROM, SRAM and SDRAM areas can be EDAC-protected using a (39, 7) BCH code

NAND Flash

NANDFCTRL2 is a VHDL IP core implementing a NAND flash memory controller designed to operate with ONFI 4.0 devices and providing DMA transfers to and from the NAND flash memory.

SPI Memory Controller

SPIMCTRL maps a memory device connected via the Serial Peripheral Interface (SPI) into AMBA AHB address space. The core is highly configurable and supports most SPI Flash memory devices.

DDR2 / DDR3

FTADDR is a memory controller for DDR2 and DDR3 SDRAM memory devices. It uses a strong error correction code to achieve exceptional fault tolerance.

CCSDS 121/123 Lossless Compression

The GRSHYLOC IP enables lossless compression for multi-spectral and hyper-spectral images according to the CCSDS121 and CCSDS123 standards

FPGA Scrubber Controller

GRSCRUB is an FPGA supervisor responsible for programming and scrubbing the FPGA configuration memory to prevent the accumulation of radiation-induced errors. The GRSCRUB IP currently supports the AMD/Xilinx Kintex UltraScale and Virtex-5 FPGA families.

I²C Slave

I²C Master

The I²C master core is a simple I²C master that provides a link between the I²C bus and the AMBA APB.

I²C to AHB Bridge

The I²C slave to AHB bridge core is a I²C slave that provides a link between the I²C bus and AMBA AHB.

SPI to AHB Bridge

The SPI2AHB bridge is an SPI slave that provides a link between a SPI bus (that consists of two data signals, one clock signal and one select signal) and AMBA AHB.

SPI Controller

The SPICTRL provides a link between the AMBA APB bus and the Serial Peripheral Interface (SPI) bus. Through registers mapped into APB address space the core can be configured to work either as a master or a slave.

USB 2.0 Device Controller

The Universal Serial Bus Device controller (GRUSBDC) provides an interface between an USB 2.0 bus and an AMBA-AHB bus.

USB 2.0 Host Controller

The USB 2.0 Host Controller provides a link between the AMBA on-chip bus and the Universal Serial Bus (USB). The host controller supports High-, Full- and Low-Speed USB traffic.

USB Debug Link

The Universal Serial Bus Debug Communication Link (USBDCL) provides an interface between an USB 2.0 bus and an AMBA-AHB bus

Gbit Ethernet

The GRETH_GBIT core implements a 10/100/1000 Mbit/s Ethernet Media Access Controller (MAC) with AMBA host interface. Receive and transmit data is autonomously transferred between the Ethernet MAC and the AMBA AHB bus using DMA transfers.

Ethernet 10/100

The GRETH is a 10/100 Mbit/s Ethernet MAC controller IP with AMBA host interface

CCSDS ECSS

The CCSDS/ECSS Spacecraft Data Handling IP cores represent a collection of cores that have been developed specifically for the space sector. These IP cores implement functions commonly used in spacecraft data handling and management systems. Supporting Software Libraries and EGSE equipment are available.

CAN FD

GRCANFD is a CAN IP core implementing a CAN-FD controller compatible with both CAN 2.0 and CAN FD. GRCANFD features a DMA interface to fetch and store frames from/to external memory via AHB or AXI4 bus.

CAN 2.0B

GRCAN is a CAN 2.0 IP core that implements an internal CAN controller and an AHB DMA backend. The APB bus is used for configuration, control and status handling and the AHB bus is used for retrieving and storing CAN messages via the DMA engine.

MIL-STD-1553

The GR1553B core implements the MIL-STD-1553B (Notice 2) data bus protocol, with ability to serve as Bus Controller (BC), Remote Terminal (RT) or Bus Monitor (BM).

PCI Bridge

The GRPCI2 IP core provides a 32-bit master/target interface for AMBA AHB-2.0 systems

SpaceWire CODEC

The GRSPW_CODEC core implements a SpaceWire encoder-decoder with a 9-bit wide FIFO host interface in each direction. The core complies to the SpaceWire standard (ECSS-E-ST-12C).

SpaceWire node

The GRSPW2 core implements a SpaceWire link controller with SpaceWire RMAP support and AMBA host interface.

SpaceWire Router

The GRSPWROUTER IP core is a VHDL model of a SpaceWire routing switch as defined in the ECSS-E-ST-50-12C standard. The core is highly configurable, flexible and portable to a wide variety of FPGA and ASIC technologies.

SpaceFibre and WizardLink Interface

The GRHSSL IP Core is a versatile and highly configurable high-speed serial link controller written in VHDL, capable of implementing a SpaceFibre IP Core (GRSPFI), a WizardLink IP Core (GRWIZL), or both within a single solution.

LEON-CERTUS/PRO

Prebuilt bitstreams for the CertusPro-NX Versa Board and for the Certus-NX Versa Evaluation Board, intended for evaluation of software running on a LEON3 SoC.

LEON-XCKU

Prebuilt bitstreams of the Xilinx Kintex UltraScale FPGA KCU105 Evaluation Kit. These bitstreams are intended for evaluation of software running on a LEON5 SoC.

LEON-PF

Prebuilt bitstreams of the Microchip PolarFire FPGA Splash Kit. These bitstreams are intended for evaluation of software running on a LEON5 SoC.

LEON-V5QV

We provide prebuilt bitstreams of the Xilinx ML510 development board, considered to be a good commercial option for prototyping with the space-grade Xilinx Virtex-5QV FPGA. These bitstreams are intended for evaluation of software running on a LEON3 or LEON4 SoC.

LEON-RTG4

Prebuilt bitstreams for the Microsemi RTG4 Development Kit. These bitstreams are intended for evaluation of software running on a LEON3 or LEON4 SoC implemented in RTG4.

LEON3

The LEON3 processor offers robust fault tolerance and performance for space and high-reliability applications, including satellites and scientific instruments.

LEON4

The LEON4 processor builds on the success of its predecessors, providing enhanced performance and efficiency for demanding space and high-reliability applications.

LEON5

The LEON5 sets a new standard with exceptional processing and fault tolerance capabilities, perfect for advanced payloads and platform units in extreme environments.

NOEL-ARTYA7

Prebuilt bitstreams of the Arty A7 (Artix-7 FPGA Development Board). These bitstreams are intended for evaluation of software running on a NOEL-V RISC-V SoC.

NOEL-XCKU

Prebuilt bitstreams of the AMD/Xilinx Kintex UltraScale FPGA KCU105 Evaluation Kit. These bitstreams are intended for evaluation of software running on a NOEL-V RISC-V SoC.

NOEL-PF

Prebuilt bitstreams of the Microchip PolarFire FPGA Splash Kit. These bitstreams are intended for evaluation of software running on a NOEL-V RISC-V SoC.

NOEL-V

The NOEL-V is a synthesizable VHDL model of a processor that implements the RISC-V architecture. The NOEL-V can be implemented as a dual-issue processor, allowing up to two instructions per cycle to be executed in parallel.

GRLIB Xilinx

GRLIB Microchip

GRLIB NanoXplore

GRLIB Lattice

TSIM3-GR765

TSIM3-GR765 is an instruction-level simulator capable of emulating the GR765 octa-core microprocessor in RISC-V NOEL-V and SPARC LEON5 mode. The simulator includes features such as non-intrusive debugging, profiling, tracing and instruction level code coverage.

GR716B-MIDI

Compact evaluation platform for the GR716B mixed-signal rad hard microcontroller and the CertusPro-NX FPGA.

GRMON4

The most recent version of our GRMON debug tool provides complete control over SPARC LEON and RISC-V NOEL processors with enhanced features like advanced breakpoints, GUI, and support for JTAG, Ethernet, and SpaceWire debug connections.

LEON/NOEL C/C++ IDE

We provide a quick-start guide on how to set up the Eclipse framework or Microsoft Visual Code to be used for the development of LEON/NOEL-V applications, together with a GCC tool-chain.

TSIM2

TSIM2 is an instruction-level simulator capable of emulating ERC32- and LEON2/3/4-based single-processor systems, such as GR712RC (one processor emulated), UT699, UT699E, UT700, AT697 and AT7913E (Spw-RTC).

TSIM3

Instruction-level simulator capable of emulating single- and multi-core processor systems based on the LEON2/3/4 processors with high simulation accuracy. It is highly user-extensible, includes functionalities such as a scriptable Tcl frontend, GDB support, and using TSIM as a library. TSIM3 also includes features such as non-intrusive debugging, profiling, tracing and instruction level code coverage.

GRMON2

An older version of our debug monitor. It offers robust control and debugging capabilities for LEON cores and various interface options.

GRMON3

The previous version of our GRMON debug tool. It provides complete control over LEON and NOEL cores with enhanced features like advanced breakpoints, GUI, and multi-interface support including JTAG, Ethernet, and USB.

TM/TC EGSE

The EGSE is ideally suited for the verification of FPGA designs and validation of ASIC devices, as well as during the integration of complete TM/TC boards or communication subsystems.

GRESB SpaceWire/Ethernet Bridge

The GRESB is a SpaceWire/Ethernet Bridge with routing capabilities that facilitates rapid development and testing of equipment with SpaceWire interfaces.

GR-CPCI-XC7K

AMD/Xilinx Kintex-7 FPGA development board in compact PCI, 6U, 2 slots format.

GR-VPX-XCKU060

OpenVPX compatible, 6U format, Payload profile development board with an AMD Kintex Ultrascale 060 FPGA.

GR-CPCIS-XCKU

AMD/Xilinx Kintex Ultrascale FPGA development board. Designed in 6U CPCI-S format.

GR718B-BOARD

Development board for the GR718B Radiation-Tolerant 18x SpaceWire router, designed in 6U Compact PCI format.

GR-CPCI-GR716-DEV

Interface board in 6U CPCI format, to be used with the GR716-BOARD. Provides access to all interfaces and additional extension options.

GR716-BOARD

Evaluation Board intended for rapid evaluation of the GR716 rad hard microcontrollers.

GR716-MINI

Very compact (50mm x 35mm) evaluation platform for the GR716 mixed-signal rad hard microcontrollers.

GR712RC-BOARD

Development board for the GR712RC dual-core fault-tolerant LEON3FT SPARC V8 processor. Designed in a Double Eurocard format.

GR740-MINI

Compact evaluation platform designed to showcase the capabilities of the GR740 SoC and the CertusPro-NX FPGA.

GR-VPX-GR740

Development board for the GR740 quad-core 32-bit fault-tolerant LEON4FT SPARC V8 processor. Designed in 6U OpenVPX format.

GR-CPCI-GR740

Development board for the GR740 quad-core fault-tolerant LEON4FT SPARC V8 processor. Designed in 6U Compact PCI format.