GRLIB IP Library - Lattice support
The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SoC) development. The modular SoC designs are built from IP cores with common on-chip bus interfaces and use a coherent method for simulation and synthesis. The library is vendor-independent, with support for different CAD tools and target technologies. A unique plug&play method is used to configure and connect the IP cores without the need to modify any global resources. The library includes several processor models, including the fault-tolerant LEON3FT 32-bit SPARC V8 and the NOEL-V RISC-V processor models.
Designs based on the GRLIB IP library are highly portable between target technologies. The library infrastructure provides project generation support for the Lattice Radiant software environment.
GRLIB contains template designs for several FPGA boards (the set of included template designs changes with type of GRLIB distribution). A list of supported boards is available in the GRLIB IP Library User's Manual.
The area of the different IPs in Lattice FPGAs is available in the grlib_area, a spreadsheet for SoC area estimation.
GRLIB documentation and downloads are available via the GRLIB IP Library product page.
Contact us if you want to evaluate GRLIB on Lattice FPGAs.
GRLIB IP cores supported in Lattice FPGAs
TIMER, GPIO, UART
On-chip RAM with FT
(Quad) SPI Memory Controller
FTMCTRL (PROM/SRAM/SDRAM & I/O)
NANDFCTRL2 (NAND Flash)
Level 2 Cache
AMBA AHB Controller
AMBA APB Controller
AMBA AHB to AHB Bridge
AMBA AHB to AXI Bridge
CAN & CANFD
I2C & SPI