Cobham Gaisler AB provides IP cores and supporting development tools for embedded processors based on the SPARC architecture. We specialize in digital hardware design for both commercial and aerospace applications

Serial Peripheral Interface

The Serial Peripheral Interface (SPI) bus is a synchronous serial data link typically consisting of two data lines, one clock line, and one or several slave select signals, allowing full-duplex data transfers. Variants with one bi-directional data line that allows half-duplex transfers, and simplex links also exist. Aeroflex Gaisler provides several SPI cores:

  • SPICTRL - SPI master/slave controller core, supporting several SPI variants and all SPI modes.
  • SPI2AHB   - SPI to AHB bridge. Acts as a slave on SPI bus and translates SPI accesses to AHB accesses.
  • SPIMCTRL   - SPI memory controller that maps a SPI Flash memory device into AMBA address space