GR765 Octa-Core Processor

Introduction

The GR765 is the next-generation radiation-hardened fault-tolerant octa-core system-on-chip, with the bootstrap option to select between LEON5FT SPARC V8 and NOEL-V RV64 RISC-V processor cores. It supports DDR3 SDRAM and NAND Flash memory with advanced error detection and correction capabilities. The communication interfaces include a SpaceWire router, SpaceFibre, Ethernet, MIL-STD-1553, and CAN-FD interfaces. 
This page describes a running development and no guarantees can be given concerning future product availability. All information on this page is subject to change without notice.
GR765 block diagram
Specification
  • Processor target frequency: 1 GHz
  • Target technology: STM 28nm FDSOI
  • TID immunity: 50 Krad
  • Main memory interface: DDR3 SDRAM, DDR4 SDRAM TBD

Features

  • 8x Fault-tolerant LEON5FT or NOEL-V FT with dedicated FPU and MMU
  • 32 KiB per core L1 cache, connected to advanced interconnect providing multiple-parallel paths between processors and Level-2 Cache
  • 2+ MiB L2 cache, 512-bit cache line, 4-ways
  • DDR3 SDRAM, DDR4 SDRAM TDB, interface with dual x8 device correction capability
  • DMA controllers
  • SpaceFibre x4+ lanes 6.25 Gbit/s, simpler protocols (Wizard link), PCIe TBD
  • 12-port SpaceWire router with +4 internal ports
  • 3x 10/100/1000 Mbit Ethernet with TT Ethernet support. TSN support TBD.
  • 2x MIL-STD-1553B
  • 2x CAN-FD
  • 12 x UART
  • 2x SPI master/slave, GPIO, Timers & Watchdog
  • 2x I2C interface
  • NAND Flash controller interface
  • FPGA Supervisor interface
  • SoC Bridge interface for efficient connection to companion FPGAs
  • High-pin count – LGA1752 (TBD)
  • Debug links: Ethernet, JTAG, SpaceWire
Applications
The GR765 is targeted at high-performance general purpose processing with support for mixed-criticality applications. The architecture is suitable for both symmetric and asymmetric multiprocessing and contains design extensions to provide hardware support for isolation between mixed-criticality applications.

Software Support

The GR765 is immediately supported by development tools such as the GRMON software debugger and various compilers and operating systems and a flight-quality boot loader for flight.

Schedule

The full GR765 development from concept to flight model availability has the following engineering activities:

  • Phase 1 - Front end design and prototype development.
  • Phase 2 - FM development. Output: GR765-XX – GR765 prototypes without an established production test program
    • GR765-XX plastic package development
    • GR765-XX manufacturing
  • Phase 3 - Output: GR765 prototypes, triple-temp test prototypes  and flight models
    • GR765-XX electrical test
    • GR765-XX ESD tests
    • GR765-XX radiation validation
    • GR765-CP/MP/MS manufacturing (same design as GR765-XX)
    • GR765-CP/MP/MS electrical test
    • GR765-MS validation

Currently, the phase 1 development is ongoing with phase 2 planned to start in the first half of 2023.
Prototype devices will enter manufacturing in 2023.

Development Board

We can provide FPGA prototypes of the GR765 design for various FPGA platforms.

Documentation

No public documentation is available at this stage. 

Document File
GR765 Product Brief GR765 Product Brief.pdf (June 2022)
GR765 Data Sheet and User’s Manual Please contact us.