- 8x Fault-tolerant LEON5FT or NOEL-V FT with dedicated FPU and MMU
- 32 KiB per core L1 cache, connected to advanced interconnect providing multiple-parallel paths between processors and Level-2 Cache
- 2+ MiB L2 cache, 512-bit cache line, 4-ways
- DMA controllers
- SpaceFibre x4+ lanes 6.25 Gbit/s, simpler protocols (Wizard link)
- 12-port SpaceWire router with +4 internal ports
- 3x 10/100/1000 Mbit Ethernet with TT Ethernet support. TSN support TBD.
- 2x MIL-STD-1553B
- 4x CAN FD
- 12 x UART
- 2x SPI master/slave, GPIO, Timers & Watchdog
- 2x I2C interface
- NAND Flash controller interface
- FPGA Supervisor interface
- SoC Bridge interface for efficient connection to companion FPGAs
- High-pin count – LGA1752
- Debug links: Ethernet, JTAG, SpaceWire, CAN
The GR765 is targeted at high-performance general-purpose processing with support for mixed-criticality applications. The architecture is suitable for both symmetric and asymmetric multiprocessing and contains design extensions to provide hardware support for isolation between mixed-criticality applications.
The GR765 is immediately supported by development tools such as the GRMON software debugger and various compilers and operating systems and a flight-quality boot loader for flight.
We can provide FPGA prototypes of the GR765 design for various FPGA platforms.
GR765 Data Sheet and User’s Manual
Please contact us.