NAND Flash Memory Controller with DMA

NANDFCTRL2 is a VHDL IP core implementing an interface to NAND flash memory devices. The memory controller is designed to operate with ONFI 4.0 flash memory devices and provides DMA transfers to and from the memory. The core implements a BCH EDAC with the capability of correcting 60 errors per chunk of 1024 bytes of data. The actual error correction capability is configured by means of VHDL generics, in conjunction with the configuration of memory support. The EDAC can be combined with a data randomizer, which breaks any repetitive bit patterns, thereby increasing memory endurance. Both the EDAC and the Randomizer can be bypassed during runtime if the user needs to access the memory without them.

 

 

To support detection and recovery from SEFI, the core provides timeout functions in addition to the EDAC. The SEFI detection functionality monitors ongoing accesses towards the flash to detect if any access is too long, which could indicate an error in the memory.

NANDFCTRL2 can optionally be implemented without an EDAC and have the functionality implemented in software in order to save hardware resources when targeting smaller devices.

For details about the actual flash memory interface, flash memory architecture and ONFI 4.0 command set please refer to the Open NAND Flash Interface specification, revision 4.0.


     
The NAND Flash controller has the following features:
  • ONFI 4.0 support
    • All mandatory ONFI 4.0 commands + optional and vendor-specific commands
    • Asynchronous / SDR data interface (all timing modes including EDO)
    • Synchronous interfaces: NV-DDR2 and NV-DDR3 (timing modes 0-9)
      • Preliminary technology-independent PHY
  • BCH EDAC with up to 60 bits correction capacity per 1024 bytes chunks of data
  • Randomization of memory data
  • Support to read flash memory soft bits to enable a software LDPC implementation
  • Fault tolerance features
  • Basic timeout-based SEFI detection and reporting
  • 8-bit data interface with support for up to 64 targets and 16 channels (16x 8 bits data channels)
  • Support for up to 64 targets and 16 channels (16x 8 bits data channels)
  • Integrated multi-plane support
 

Targets

The memory controller has been tested with the UT81NDQ512G8T, the 69F256G16, and the 3DFN128G08US8761 NAND flash memories.

Availability

NANDFCTRL2 is part of the GRLIB IP Library and can be licensed as a separate add-on.

The current version of the core is suitable for users who want to include NANDFCTRL2 in products and is suitable for both ASIC and FPGA implementations.

For specific information related to Xilinx, Microchip, and Lattice FPGAs, please refer to our dedicated web pages:

- Specific support for Lattice FPGAs

- Specific support for Microchip FPGAs

- Specific support for Xilinx FPGAs

 

 The IP is suitable for SLC-based flight-grade Raw NAND Flash interfaces, with the exception for the flight assurance related to the FPGA PHY implementation.

Future implementations are pending customer demands and include hardware LDPC ECC for supporting MLC and TLC modes.

 

 

LEON3-XCKU-NANDFCTRL2-EX Example Design

The LEON3-XCKU-NANDFCTRL2-EX is an example bitstream for the Xilinx KCU105 Evaluation Kit interfacing with the Frontgrade UT81NDQ512G8T mezzanine board.

To get access to the evaluation bitstream, contact sales@gaisler.com.

Contact your local Frontgrade representative to get access to the UT81NDQ512G8T mezzanine board.

 

Documentation 

 Document  File
NANDFCTRL2 IP Core User's Manual

 grip.pdf (See section NANDFCTRL2)

NANDFCTRL2 FPGA Resources Utilization

 grlib_area.xls (See NANDFCTRL2-EX sheet)

LEON3-XCKU-NANDFCTRL2 Example Bitstream User's Manual

 LEON3-XCKU-NANDFCTRL2-EX-UM.pdf

LEON3-XCKU-NANDFCTRL2 Example Bitstream Quick Start Guide

 LEON3-XCKU-NANDFCTRL2-EX-QSG.pdf