NAND Flash

The IP can communicate with multiple parallel NAND flash memory devices. The core provides an AMBA AHB master to perform data write and read accesses. Configuration through generics supports a vast variation of memory devices including support for up to 64 individually addressable targets via chip enable signals, 32 ready-busy signals and 16 channels.

For details about the actual flash memory interface, flash memory architecture and ONFI 4.0 command set please refer to the Open NAND Flash Interface specification, revision 4.0.

The memory controller has been tested with the UT81NDQ512G8T, the 69F256G16, and the 3DFN128G08US8761 NAND flash memories.

The IP can be implemented in any ASIC or FPGA technology. For specific information related to Xilinx, Microchip, and Lattice FPGAs, please refer to our dedicated web pages:

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- Specific support for Lattice FPGAs
- Specific support for Microchip FPGAs
- Specific support for Xilinx FPGAs

Estimation of the resource utilization can be found in the download files below (Excel sheet for SoC area estimation).

The IP core is available as a separate package or as an addition to commercial versions of the GRLIB VHDL library.

Contact sales@gaisler.com for licensing information

LEON3-XCKU-NANDFCTRL2-EX example Design

The LEON3-XCKU-NANDFCTRL2-EX is an example bitstream for the Xilinx KCU105 Evaluation Kit interfacing with the Frontgrade UT81NDQ512G8T mezzanine board.

Documentation of the example design (User's manual and Quick Start Guide) are freely available for download in the Downloads section of this webpage. To get access to the evaluation bitstream, contact sales@gaisler.com

Contact your local Frontgrade representative to get access to the UT81NDQ512G8T mezzanine board.