Cobham Gaisler AB provides IP cores and supporting development tools for embedded processors based on the SPARC architecture. We specialize in digital hardware design for both commercial and aerospace applications

CAN-FD

GRCANFD is a VHDL IP core implementing a CAN-FD controller compatible with both CAN 2.0B and CAN-FD. It consists of an internal CAN-FD codec and a top layer handling the configuration and control of the IP. GRCANFD features a generic bus master interface to fetch and store frames from/to external memory. Wrappers for adapting the generic bus master to AMBA 2.0 AHB and AXI4 are available. The IP core also features an AMBA 2.0 APB slave interface for accessing the configuration registers.

The codec is compliant with the ISO standard for CAN-FD: 11898-1:2015 (2nd edition). It implements the functionality related to the PL and MAC sub-layers of the protocol: transmission, reception and acknowledgment of frames, bit synchronization, CRC calculation, error detection and signaling, arbitration control, frame encoding, etc. It supports both classical CAN and CAN-FD frames, including all the types (Data, Remote, Error and Overload Frames) and formats (CBFF, CEFF, FBFF and FEFF) specified in the standard.

The Transmit and Receive Channels operate separately. GRCANFD includes an internal SRAM for buffering frames for both channels. For the Transmit Channel, GRCANFD fetches frames from the external memory and stores them internally into the local SRAM; frames are then transmitted by the codec. For the Receive Channel, the codec verifies and acknowledges the frames, and GRCANFD filters and stores them into the local SRAM; once a full frame is available, GRCANFD writes it to the external memory. The communication with the external memory is based on a DMA engine through the generic bus master interface.

Key FeaturesGRCANFD block diagram

  • Compatible with both CAN 2.0B and CAN-FD
  • Fully compliant with ISO 11898-1:2015
  • Based on the existing GRCAN IP for maintaining backwards compatibility
  • Generic bus master interface for frame fetching and storage with DMA
  • Optional wrappers for AMBA 2.0 AHB and AXI4
  • AMBA 2.0 APB slave interface for configuration of the IP
  • Independent Transmit and Receive channels
  • Local SRAM for frame buffering
  • Frame Acceptance Filter (Receive Channel)
  • Frame Synchronization Filters (Transmit and Receive Channels)
  • Transmitter Delay Compensation of up to 2 data bit times (data bit-rate only)
  • Listen-only mode
  • Single-shot mode
  • CAN bus redundancy