GRCANFD is a VHDL IP core implementing a CAN-FD controller compatible with both CAN 2.0 and CAN-FD. It consists of an internal CAN-FD codec and a top layer handling the configuration and control of the IP. GRCANFD features a generic bus master interface to fetch and store frames from/to external memory. Wrappers for adapting the generic bus master to AMBA 2.0 AHB and AXI4 are available. The IP core also features an AMBA 2.0 APB slave interface for accessing the configuration registers.

The codec is compliant with the ISO standard for CAN-FD: 11898-1:2015 (2nd edition). It implements the functionality related to the PL and MAC sub-layers of the protocol: transmission, reception and acknowledgment of frames, bit synchronization, CRC calculation, error detection and signaling, arbitration control, frame encoding, etc. It supports both classical CAN and CAN-FD frames, including all the types (Data, Remote, Error and Overload Frames) and formats (CBFF, CEFF, FBFF and FEFF) specified in the standard.

The Transmit and Receive Channels operate separately. GRCANFD includes a FIFO for each channel in order to temporarily buffer frames; the size of these FIFOs can be individually configured via VHDL generics. For the Transmit Channel, GRCANFD fetches frames from the external memory and stores them internally into the TX FIFO; frames are then transmitted by the codec according to the CAN-FD standard. For the Receive Channel, the codec verifies and acknowledges the frames, and GRCANFD filters and stores them into the RX FIFO; once a full frame is available, GRCANFD writes it to the external memory. The communication with the external memory is handled by an autonomous DMA engine transferring frames over the generic bus master interface.

Key FeaturesGRCANFD block diagram

  • Support for both CAN 2.0 and CAN-FD
  • Fully compatible with ISO 11898-1:2015
  • Based on the existing GRCAN IP for maintaining backwards compatibility
  • Generic bus master interface for frame fetching and storage with DMA
  • Optional wrappers for AMBA 2.0 AHB and AXI4
  • AMBA 2.0 APB slave interface for configuration and control of the IP
  • Independent Transmit and Receive channels
  • Local FIFOs with configurable depth for Receive and Transmit channels
  • Frame Acceptance Filter (Receive channel)
  • Frame Synchronization Filters (Transmit and Receive channels)
  • Single shot mode (Transmit channel)
  • Optional generation of Overload Frames (Receive channel)
  • Transmitter Delay Compensation of up to 2 data bit times (data bit-rate only)
  • Listen-only, Self-ACK and Loop-back modes
  • CAN bus redundancy
  • Overload frame generation when RX FIFO is full
  • Support for CANOpen Minimal Set Protocol as per the
    ECSS-E-ST-50-15C specification, section 9


Area and timing

 GRCANFD is inherently portable and can be implemented on most FPGA and ASIC technologies. 

For specific information related to Xilinx, Microchip, and Lattice FPGAs, please refer to our dedicated web pages:

- Specific support for Lattice FPGAs

- Specific support for Microchip FPGAs

- Specific support for Xilinx FPGAs

Estimation of the resource utilization for GRCANFD can be found here:

Excel sheet for SoC area estimation

The GRCANFD core can be licensed commercially, either stand-alone or as part of the GRLIB IP library.