Cobham Gaisler is a world leader in embedded computer systems for harsh environments, with footprints in many parts of the solar system. We provide the full ecosystem to support digital hardware design for mission critical System-on-a-Chip solutions. The IP cores and development tools support processors based on the SPARC and RISC-V architectures. In addition to this, a number of standard components are available.

GR-VPX-GR740 Quad-Core LEON4FT Development Board

The GR-VPX-GR740 development board has been designed to support the development and fast prototyping of systems based on the Cobham Gaisler GR740 quad-core 32-bit fault-tolerant LEON4FT SPARC V8 processor. With the GR-VPX-GR740 Development Board Cobham Gaisler introduces a high performance Single-Board Computer for use within  OpenVPX and SpaceVPX environments.

Based on the Cobham Gaisler GR740 Quad-Core 32-bit LEON4FT SPARC V8 processor, the GR-VPX-GR740 board comes in a 6U VPX format (233.5 mm x 160 mm) and is intended for use in OpenVPX chassis occupying a 1” slot (including mezzanine board). The board can also be used in stand-alone operation with a single 12V supply, in this case with limited VPX functionality.

The board is equipped with on-board memories for boot and application storage, and an SODIMM for SDRAM. The front panel includes basic communication interfaces and LED indicators, whereas the rear connectors are intended for OpenVPX/SpaceVPX backplane connections.

The current GR-VPX-GR740 product includes a simple mezzanine board GR-VPX-SPW-MEZZ which provides two SpaceWire interfaces on the front panel. This mezzanine board does not include all the mezzanine interfaces provided by the main board. The mezzanine interfaces supported by the main board are listed to provide information for the users who can build their own mezzanine boards. Currently, this board product is not provided with any other mezzanine board other than the GR-VPX-SPW-MEZZ.

The main board supports the following mezzanine interfaces (which can be utilized by the users to build their own mezzanine cards):  A HPC-400 FMC connector for FPGA or other mezzanine boards provides interfaces with PCI, 2xSpaceWire and GPIO of the processor. It also connects to the Data Plane of the backplane via two Fat Pipes (8 differential pairs each) and four Thin Pipes (4 differential pairs each). Further signals routed between the mezzanine connector and the backplane include two Thin Pipes to the Control Plane and other system control signals. Note: Among these mezzanine interfaces, the GR-VPX-SPW-MEZZ mezzanine board make use of the two SpaceWire interfaces to provide two Front panel SpaceWire interfaces.

The board is developed to be used as a Switch Module in the OpenVPX architecture based on ANSI/VITA 65.0-2017. It can also be ordered as a factory-configured variant with the backplane interface designed as a Switch and Controller Module providing some of the features of the SpaceVPX architecture specified in the Draft ANSI/VITA 78.00-2015. See details in the Product Sheet. 



    • GR740 quad-core 32-bit fault-tolerant LEON4FT SPARC V8 processor
    • On-board memory:
      • SDRAM SODIMM module - 256 MiB modules provides 128 MiB of accessible data RAM plus ECC check bits.
      • Parallel Boot MRAM 128 KiB & SPI Flash memory 32 MiB
    • Power, reset, clock and auxiliary circuits
    • Interfaces at front edge of board:
      • MIL-STD-1553B Interface (Transceiver/Transformer and D-sub 9)
      • RJ45 10/100/1000 Mbit GMII/MII Ethernet interface (KSZ9021GN)
      • 8-bit General purpose I/O (2x5 pin DIL header) 
      • UART/JTAG interface using FTDI Serial-USB converter (FT4232HL/USB-uAB)
      • PPS (Pulse Per Second) input for synchronization (SMB)
      • LED indicators for power, error, watchdog and PLL lock
      • Push button switch for reset
    • Interfaces at back edge of board:
        • Supply and system control (VPX P0)
        • SM bus*
        • 8 SpaceWire interfaces (VPX P1)
          • 6 fully supported on-board, available from the GR740 SpW Router
          • 2 routed between backplane and FMC connector*
        • User Defined (UD) signals from GPIO (VPX P2)
        • User Defined (UD) signals from GPIO (VPX P3)
        • 1 Fat Pipe and 2 Thin Pipes for high-speed serial data interfaces (VPX P3)*
          • Routed between backplane and FMC connector, functionality to be implemented in mezzanine board*
        • 1 Fat Pipe and 2 Thin Pipes for high-speed serial data interfaces (VPX P5)*
          • Routed between backplane and FMC connector, functionality to be implemented in mezzanine board*

On-board mezzanine interface:

    • HPC-400 FMC connector
    • 2 SpaceWire interfaces connected to the GR740 router
    • 2 Thin Pipes routed to P1 on the back edge (used for 2 SpaceWire interfaces)*
    • 2 Fat Pipes and 4 Thin Pipes routed to P3 and P5 on the back edge*
    • 1 SpaceWire interface to on-board MDM9S connector*
    • SM bus*
    • PCI interface (32-bit) from the GR740*
    • 10-bit General purpose I/O from the GR740*
    • Additional backplane clocks*
    • +12V supply

*Note: These interfaces are available on the main board and interfaced with the mezzanine connector. Currently, the mezzanine board delivered along with this product do not support and do not make use of such interfaces. These interfaces are listed to provide information for the users who can build their own mezzanine boards.


Document File
GR740 device information GR740 product page
GR-VPX-GR740 Product Sheet alt GR-VPX-GR740-PS.pdf
GR-VPX-GR740 User's Manual alt GR-VPX-GR740-UM.pdf
GR-VPX-GR740 Quick Start Guide altGR-VPX-GR740-QSG.pdf
GR-VPX-GR740 Quick Start Guide Board Package