The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SoC) development. The modular SoC designs are built from IP cores with common on-chip bus interfaces and use a coherent method for simulation and synthesis. The library is vendor-independent, with support for different CAD tools and target technologies. A unique plug&play method is used to configure and connect the IP cores without the need to modify any global resources. The library includes several processor models, including the fault-tolerant LEON3FT 32-bit SPARC V8 and the NOEL-V RISC-V processor models.
Contact us if you want to evaluate GRLIB on NanoXplore FPGAs
Template designs are available for NanoXplore FPGAs. The library infrastructure provides project generation support for the NanoXplore Impulse software environment.
The area of the different IPs in NG-Medium and NG-Ultra FPGAs is available in the grlib_area, a spreadsheet for SoC area estimation.
GRLIB IP cores supported in NanoXplore FPGAs
TIMER, GPIO, UART
On-chip RAM with FT
(Quad) SPI Memory Controller
FTMCTRL (PROM/SRAM/SDRAM & I/O)
NAND Flash Controller
AMBA AHB Controller
AMBA APB Controller
AMBA AHB to AHB Bridge
CAN & CANFD
I2C & SPI