We are a world leader in embedded computer systems for harsh environments, with footprints in many parts of the solar system.
We provide the full ecosystem to support digital hardware design for mission critical System-on-a-Chip solutions. The IP cores and development tools support processors based on the SPARC and RISC-V architectures. In addition to this, a number of standard components are available.
Ready to be challenged? We are hiring!
Are you curious about starting a new engaging role, at a world-leading company that works towards European Space Agency and NASA? Then this is your opportunity. We looking for a Software and Hardware developers. We welcome your application!
Access career page or contact us through career (at) gaisler.com.
SPARC or RISC-V? LEON or NOEL-V?
Ever wonder which microprocessor to use in your space system design?
Check out this white paper which discusses the differences between LEON/SPARC and NOEL-V/RISC-V architectures. The paper describes our past and ongoing component development and explains the rationale for some architectural design choices for future roadmap products. Included herein are trends in the Space industry that are driving key new features example application use-cases and tradeoffs from a software perspective of a legacy LEON/SPARC design vs. a new RISC-V architecture.
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RISC-V Processor Model - NOEL-V
The NOEL-V is a synthesizable VHDL model of a processor that implements the open RISC-V architecture from the RISC-V International organization.
This is the first released model in the RISC-V product line of processors. Seven different configurations are now available for NOEL-V, ranging from a tiny 32-bit version to a 64-bit high performance version. NOEL-V complements the LEON line of processors.
Click here for more information.
Rad-Hard Dual-Core Processor
Dual-Core LEON3-FTGR712RC Radiation-hard Dual-Core LEON3-FT Processor, 200 MIPS, 200 MFLOPS |
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Rad-Hard Quad-Core System-on-Chip
Quad-Core LEON4-FTGR740 Radiation-hard Quad-Core LEON4-FT Processor, 1000 MIPS, 1000 MFLOPS, QML-V/QML-Q |
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 GR740 CG625 |
The GR740 component has received QML-V and QML-Q quality certification by DLA in Q2 2022. Access the GR740 SMD 5962-21204.
Rad-Hard Quad-Core System-on-Chip - Plastic
Quad-Core LEON4-FTGR740-PBGA Plastic Radiation-hard Quad-Core LEON4-FT Processor, 1000 MIPS, 1000 MFLOPS |
Vacancy Notice
We are currently looking for experienced ASIC/FPGA developers and verification engineers to join our team ... read more.
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Latest Releases
| NOEL-V processor model LEON5 processor model GRLIB IP Library 2022.1-b4272 GR712RC user's manual 2.14 GR712RC data sheet 2.4 GR740 user's manual 2.5 GR716 data sheet 2.0 GR718B user's manual 3.7 |
GRMON3 Debug Monitor 3.2.15 GRMON2 Debug Monitor 2.0.99 TSIM3 LEON Simulator 3.1.6 TSIM2 LEON/ERC32 Simulator 2.0.66 BCC Bare-C Compiler 2.2.1 RCC RTEMS Compiler 1.2.25, 1.3.1 VxWorks 7 support for LEON VxWorks 6.9 support for LEON |
LEON and NOEL FPGA Evaluation Designs
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LEON/GRLIB examples for Lattice Certus/Pro-NX-RT |
Embedded World 2022
CAES is sponsor, presenter and exhibitor in the RISC-V International's booth at Embedded World 21-23 June 2022, in Nuremberg, Germany. CAES will present the "NOEL-V, a Configurable 32-Bit and 64-bit RISC-V IP".
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HiPEAC 2022
CAES is co-hosting the De-RISC workshop during HiPEAC on 20 June, 2022, in Budapest, Hungary. The De-RISC (Dependable Real-time Infrastructure for Safety-critical Computer) project addresses computer systems within the space and aviation domains. De-RISC is a project where an international consortium will introduce a hardware and software platform based around the RISC-V ISA. The work in this project is to productize a multi-core RISC-V system-on-chip design already owned by CAES and to port the XtratuM hypervisor owned by fentISS to that design to create a full platform consisting of hardware and software for future European developments within space and aeronautical applications.
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QML-V and QML-Q Space Grade Qualification of the GR740 Quad-Core LEON4FT Microprocessor
Our Fault-Tolerant GR740 Quad-Core LEON4FT microprocessor device has successfully completed Defense Logistics Agency (DLA) qualification and can continue to meet some of the most demanding processing challenges of future space missions, with the added assurance of QML pedigree.
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CAES and Ashling announce Ashling’s RiscFree™ C/C++ Toolchain for CAES’ NOEL-V® Processors
Ashling and CAES announced today that Ashling’s RiscFree Toolchain will provide software development support for CAES’ NOEL-V fault tolerant RISC-V based processors. RiscFree is Ashling’s Integrated Development Environment (IDE) including a Compiler and Debugger and provides software development and debug support for NOEL-V.
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SEE/MAPLD 2022
CAES is exhibiting at the Single Event Effects (SEE) Symposium and Military and Aerospace Programmable Logic Devices (MAPLD) combined workshop. Our colleague from Gothenburg is presenting the "GR765 LEON5FT System-on-Chip: Results of First STM 28nm Test Chip Radiation Test Campaign" paper. The GR765 is a future system-on-chip product in development that provides a octa-core fault-tolerant LEON5FT SPARC V8 processor system, 12-port SpaceWire router, 10/100/1000 Mbit Ethernet interfaces, high-speed serial links, embedded FPGA fabric and CAN-FD interfaces.
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DASIA (Data Systems In Aerospace) 2022
This year's DASIA (Data Systems In Aerospace) virtual conference is sponsored by CAES. Our colleagues will be presenting two papers at the DASIA this year: "GR765-LEON5FT Multi-Processor SoC" and "GOMX-5 APPs - The Advanced Payload Processors IOD for the GOMX-5 Mission". We are also participating in the "Artificial Intelligence for High-performance Human Space Flight Avionics Systems" paper being presented at the conference.
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4S Symposium 2022
Our colleagues will be presenting a paper at the 4S Symposium this year, "GOMX-5 APPs - The Advanced Payload Processors IOD for the GOMX-5 Mission". The Advanced Payload Processors (APPs) was developed targeting in-orbit demonstration (IOD) in the GOMX-5 mission. GOMX-5 is a flight demonstration for next generation cubesat missions, which will demand advanced attitude control, large processing capabilities, and high throughput data exchange between space and ground segments.
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Collaboration with Lattice Semiconductor to provide Radiation-Tolerant FPGAs for distributed satellite computing applications
CAES, a leading provider of mission critical electronics for aerospace and defense, and Lattice Semiconductor Corporation, the low power programmable FPGA leader, announce today an agreement whereby CAES will qualify and sell radiation-tolerant Lattice FPGAs for space and satellite applications. We are actively developing a port of our proven GRLIB development environment and a library of configurable, standardized soft IP design cores to further support customer needs as they integrate these FPGAs into their designs. This will include our new fault-tolerant NOEL-V processor soft IP core implementing the RISC-V International instruction set architecture.
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Awarded ESA contract to develop RISC-V based System-on-Chip for space applications
We have been awarded a contract with the European Space Agency (ESA) to develop a fault- and radiation-tolerant system-on-chip. Funded by the Swedish National Space Agency, the project will improve performance and power efficiency in satellite and spacecraft applications by developing a 16-core, space-hardened microprocessor based on the open RISC-V instruction set architecture (ISA). The GR7xV processor is based on the NOEL-V processor IP core and will be designed into spaceborne controls and payload data management and processing systems to enable new kinds of observational, communication, navigational and scientific missions and services. These include advanced, flexible telecommunications satellite payloads, scientific and earth-observation payloads and robotics systems such as planetary exploration rovers.
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Contract from Vinnova to Advance High Performance RISC-V Space Computing
We have been awarded a contract from Vinnova, a Swedish government agency dedicated to promoting innovation, to develop next generation RISC-V based space computing capabilities. The results from this development will allow future microprocessors to enable spacecraft control, create high performance payload processing and will feature timing isolation for software applications and prevent interference from other parts of the system. The new NOEL-V fault-tolerant, 64-bit processor core is based on the open RISC-V instruction set architecture and builds upon our heritage with the SPARC/LEON architecture. It marks the newest addition to our trusted fault tolerant space computing product portfolio.
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Contract signed with the European Space Agency for New Advanced Space Processor
As a leader in advanced mission-critical electronics, we announced today that we have received a contract from the European Space Agency (ESA) to fund the first phase to develop a new advanced processor for space applications. Developed in Sweden and based on the popular LEON5FT Fault Tolerant Processor Core, the GR765 Microprocessor meets market demand for high-performing processors, offering a higher level of integration with more functionality on the chip to reduce weight and keep power consumption low.
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