We are a world leader in embedded computer systems for harsh environments, with footprints in many parts of the solar system.
We provide the full ecosystem to support digital hardware design for mission critical System-on-a-Chip solutions. The IP cores and development tools support processors based on the SPARC and RISC-V architectures. In addition to this, a number of standard components are available.
GR740 User Day 2022
The first GR740 User Day back in 2019 was such a success that we have decided to arrange a second one this year with brand new speakers and exciting news to be announced. The GR740 User Day 2022 will take place on Tuesday 13 December 2022 in the ERASMUS Auditorium at ESTEC in Noordwijk, The Netherlands.
The User Day will be collocated with the ESA RISC-V In Space Workshop that will take pace on Wednesday 14 December 2022.
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GR740 User Day 2022 - US Event
For our US customers we are arranging a virtual online GR740 User Day - US Event in the morning (11am Eastern Time) of Thursday 15 December 2022. The virtual event will feature a handful dedicated new live presentations and be limited to two hours, followed by the release of the recorded presentations from the preceding European event.
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Ready to be challenged? We are hiring!
Are you curious about starting a new engaging role, at a world-leading company that works towards European Space Agency and NASA? Then this is your opportunity. We are looking for an experienced Supply Chain Engineer, experienced ASIC/FPGA Engineers, experienced Embedded Software and Tools Engineers, a Sales Assistant, and a Receiving and Shipping Engineer and are continuously looking for experienced hardware and software engineers. We welcome your application!
Access our career page or contact us through career (at) gaisler.com.
SPARC or RISC-V? LEON or NOEL-V?
Ever wonder which microprocessor to use in your space system design?
Check out this white paper which discusses the differences between LEON/SPARC and NOEL-V/RISC-V architectures. The paper describes our past and ongoing component development and explains the rationale for some architectural design choices for future roadmap products. Included herein are trends in the Space industry that are driving key new features example application use-cases and tradeoffs from a software perspective of a legacy LEON/SPARC design vs. a new RISC-V architecture.
Access the white paper
RISC-V Processor Model - NOEL-V
The NOEL-V is a synthesizable VHDL model of a processor that implements the open RISC-V architecture from the RISC-V International organization.
This is the first released model in the RISC-V product line of processors. Seven different configurations are now available for NOEL-V, ranging from a tiny 32-bit version to a 64-bit high performance version. NOEL-V complements the LEON line of processors.
Click here for more information.
Rad-Hard Dual-Core Processor
Dual-Core LEON3-FTGR712RC Radiation-hard Dual-Core LEON3-FT Processor, 200 MIPS, 200 MFLOPS |
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Rad-Hard Quad-Core System-on-Chip
Quad-Core LEON4-FTGR740 Radiation-hard Quad-Core LEON4-FT Processor, 1000 MIPS, 1000 MFLOPS, QML-V/QML-Q |
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 GR740 CG625 |
The GR740 component has received QML-V and QML-Q quality certification by DLA in Q2 2022. Access the GR740 SMD 5962-21204.
Rad-Hard Quad-Core System-on-Chip - Plastic
Quad-Core LEON4-FTGR740-PBGA Plastic Radiation-hard Quad-Core LEON4-FT Processor, 1000 MIPS, 1000 MFLOPS |
Vacancy Notice
We are currently looking for an experienced supply chain engineer, experienced ASIC/FPGA engineers, a sales assistant, and a receiving and shipping engineer to join our team ... read more.
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Latest Releases
| NOEL-V processor model LEON5 processor model GRLIB IP Library 2022.2-b4274 GR712RC user's manual 2.15 GR712RC data sheet 2.4 GR740 user's manual 2.5 GR716 data sheet 3.2 GR718B user's manual 3.8 |
GRMON3 Debug Monitor 3.3.1 GRMON2 Debug Monitor 2.0.99 TSIM3 LEON Simulator 3.1.7 TSIM2 LEON/ERC32 Simulator 2.0.66 BCC Bare-C Compiler 2.2.2 RCC RTEMS Compiler 1.2.25, 1.3.1 VxWorks 7 support for LEON VxWorks 6.9 support for LEON |
LEON and NOEL FPGA Evaluation Designs
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LEON/GRLIB examples for Lattice Certus/Pro-NX-RT |
Design Win of RISC-V/NOEL-V IP for Idaho Scientific Secure Processor for Critical Infrastructure
We are pleased to announce that we have won a commercial license for our RISC-V/NOEL-V processor IP core with Idaho Scientific, based in Boise, Idaho. Idaho Scientific specializes in solutions that prevent hardware and software security attacks. These solutions help protect high-reliability systems that support critical infrastructure.
Read the full Press Release
RISC-V in Space Workshop
We are exhibiting and presenting at the RISC-V in Space Workshop at ESTEC, Noordwijk, The Netherlands, 14th of December 2022. Our fault-tolerant NOEL-V processor implements the RISC-V International instruction set architecture and is used in the GR765 Octa-Core development with the European Space Agency.
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D&R IP SoC Conference 2022
We are exhibiting and presenting the "RISC-V in Space" paper at the D&R IP SoC Conference 22 in Grenoble, France, 30th of November and 1st of December 2022. Our NOEL-V processor implements the RISC-V International instruction set architecture.
Access the event.
LEON3FT Technology Supports NASA’s Return to the Moon
We are pleased to announce that our LEON3FT microprocessor features prominently in the Artemis 1 mission, including the Vision Processing Unit on the Orion Spacecraft, as well as at least six of the CubeSat’s that are on board that use our processor technology. Congratulations to NASA and everyone on the Artemis team on a successful launch!
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GR712RC Microprocessor Selected by Argotec for Multiple Space Missions
We are pleased to announce that Argotec, an Italian aerospace engineering company, has selected the radiation hardened GR712RC dual-core LEON3FT SPARC V8 Microprocessor on several key space missions. Argotec selected the microprocessor for its reliability and capability. Argotec’s LICIACube (Light Italian CubeSat for Imaging of Asteroids), a six-unit CubeSat from the Italian Space Agency, was an important part of NASA’s Double Asteroid Redirection Test (DART) mission, which successfully took place in late September 2022. NASA's latest Moon-orbiting mission, Artemis I, will utilize the GR712RC. ArgoMoon, a micro-satellite developed by Argotec that employs the GR712RC in its computer, will perform autonomous visual-based proximity operations around the in-space stage of the propulsion system that sent the Orion spacecraft on a lunar trajectory.
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CAES Wins Contracts for Development of Next-Generation, Octa-Core, user-selectable CPU for Space
We are pleased to announced that we have won multiple contracts with the European Space Agency (ESA) for the development of the GR765 System-on-Chip (SOC), the first user selectable CPU for space. This next-generation, radiation-hardened device will allow users to select between the LEON5 SPARC V8 or NOEL-V RISC-V RV64 processor cores.
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Quad-Core LEON4FT Processor Selected for European Next-Generation Star Sensors
We are pleased to announce that we have signed a multi-year contract with Jena-Optronik to deliver flight grade GR740 quad-core LEON4FT SPARC V8 Microprocessor devices for its next-generation sensor products.
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Quad Core LEON4FT Processor Selected for Next-Generation On-orbit Servicing Spacecraft
CAES's latest fault tolerant GR740 quad-core LEON4FT processor will be used in the bus avionics and robotics interface of the SpaceLogistics’ Mission Robotic Vehicle (MRV) Spacecraft, and the Mission Extension POD (MEP), which will be deployed to assist in extending the life of aging satellites in space.
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QML-V and QML-Q Space Grade Qualification of the GR740 Quad-Core LEON4FT Microprocessor
Our Fault-Tolerant GR740 Quad-Core LEON4FT microprocessor device has successfully completed Defense Logistics Agency (DLA) qualification and can continue to meet some of the most demanding processing challenges of future space missions, with the added assurance of QML pedigree.
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Awarded ESA contract to develop RISC-V based System-on-Chip for space applications
We have been awarded a contract with the European Space Agency (ESA) to develop a fault- and radiation-tolerant system-on-chip. Funded by the Swedish National Space Agency, the project will improve performance and power efficiency in satellite and spacecraft applications by developing a 16-core, space-hardened microprocessor based on the open RISC-V instruction set architecture (ISA). The GR7xV processor is based on the NOEL-V processor IP core and will be designed into spaceborne controls and payload data management and processing systems to enable new kinds of observational, communication, navigational and scientific missions and services. These include advanced, flexible telecommunications satellite payloads, scientific and earth-observation payloads and robotics systems such as planetary exploration rovers.
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