Cobham Gaisler AB provides IP cores and supporting development tools for embedded processors based on the SPARC architecture. We specialize in digital hardware design for both commercial and aerospace applications

News and Events

Latest Releases

LEON/GRLIB bitstreams for RTG4
GRLIB IP Library 2020.2-b4254
GR712RC user's manual 2.13
GR712RC data sheet 2.4
GR712RC-BOARD document 0.13 GR740 user's manual 2.3
GR716 data sheet 1.31
GR718B user's manual 3.5
LEON3FT-RTAX document 1.9
RT-SPW-ROUTER document 1.2

 GRMON3 Debug Monitor 3.2.4
GRMON2 Debug Monitor 2.0.99
TSIM2 LEON/ERC32 Simulator 2.0.66
GRSIM LEON MP Simulator 1.1.56
BCC Bare-C Compiler 2.1.2
RCC RTEMS Compiler 1.2.25, 1.3-rc8
VxWorks 7 support for LEON
VxWorks 6.9 support for LEON

 

 

Cobham Gaisler joins Swedish Aerospace Industries

Cobham Gaisler AB, the Swedish subsidiary of Cobham Advanced Electronic Solutions (CAES), has recently been accepted as a member of the Swedish Aerospace Industries association. The Swedish Aerospace Industries is a non-profit association and industry organization whose purpose is to safeguard the interests of its members by representing the Swedish civil aviation and space industry on common issues where a national and industry representative association is needed, or where a joint or coordinated activity is deemed otherwise suitable.

Read the full press release.

 

 

Rymdforum 2021 to be hosted by Cobham Gaisler, Chalmers Technical University and the City of Gothenburg

The Rymdforum 2021 conference (the Swedish biennial space forum) will present news, explore trends, and open for dialogue and discussions related to space activities. The conference will take place in Gothenburg, 21-23 March 2021. Cobham Gaisler, together with the Chalmers Technical University and the City of Gothenburg, will be arranging the conference. Follow the progress of the conference on social media and on the conference web site.

@rymdforum2021 #rymdforum2021 #rymd2021

Visit the conference web site.

Xilinx

Cobham Advanced Electronic Solutions Radiation Hardened Microelectronics Support New Xilinx XQRKU060 FPGA

We have announced today that a variety of our radiation hardened (RadHard) solutions and Intellectual Property (IP) cores for space applications, provide support for the new Xilinx Radiation Tolerant (RT) Kintex UltraScale XQRKU060 Field-Programmable Gate Array (FPGA). Cobham Gaisler provides IP cores to be used with the XQRKU060.

The GRSRCUB FPGA scrubber and supervisor IP core supports programming the XQRKU060 and several periodic scrubbing modes to prevent accumulation of errors in the FPGA configuration memory.

Cobham Gaisler's GRLIB IP library that contains over 100 peripheral IP cores together with the NOEL-V RISC-V processor and the LEON3FT and LEON5FT SPARC processors have been adapted to support system-on-a-chip designs targeting the XQRKU060.

Read the full press release.

 

SELENE: Self-monitored Dependable platform for High-Performance Safety-Critical Systems

High-performance computing that employs commercial off-the-shelf components offers an alternative path to increasing the computational capability of safety-critical applications. Despite their potential in a number of domains, use of these systems is limited due to the lack of certified, reliable hardware platforms. The EU funded SELENE project aims to change this by proposing a safety-critical cognitive computing platform with self-aware and self-adaptive capabilities. Cobham Gaisler's NOEL-V processor implementing the RISC-V instruction set architecture is used in the project. 

Read more on the project page.  

 

 

Cobham Advanced Electronic Solutions’ GR712RC Processor Runs CHEOPS’ Instrument Flight Software

The first ESA S-class mission CHEOPS, which stands for CHaracterising ExOPlanet Satellite, recently lifted off on a Soyuz rocket from Europe's spaceport in Kourou. The satellite contains one payload, a 32 cm diameter on-axis telescope. The Data Processing Unit (DPU) within the Back-End Electronics (BEE) of the telescope was built by the Space Research Institute (Institut für Weltraumforschung, IWF) of the Austrian Academy of Sciences in Graz, Austria. The DPU is based on the Radiation-Hardened GR712RC LEON3FT Dual-Core Microprocessor. 

Read the full press release.  

 

See the LEON5 and NOEL-V video clip

The Gothenburg Symphony Orchestra has produced our video clip promoting the new LEON5 and NOEL-V processor IP cores that will be released on 25 December for  download into Xilinx’ Kintex UltraSCALE FPGAs. The original music score has been composed by Hans Ek who has also conducted the Gothenburg Symphony Orchestra when it was performed  as part of Kosmische Musik at the Gothenburg Concert Hall on 27 October 2018, 

 

Cobham Releases RISC-V Processor IP Core

Cobham Gaisler has announced  at the RISC-V Summit in San Jose, California, that it will release a new line of processor Intellectual Property (IP) cores that implements the RISC-V instruction set architecture (ISA). The NOEL-V processor IP core, the first product in the family, will be made available on 25 December for download into Xilinx’ Kintex UltraSCALE FPGAs.

Read the full press release.  

 

Cobham Releases LEON5 Processor IP Core

Cobham Gaisler has announced at the 12th Annual Workshop on Spacecraft Flight Software, at NASA Marshall Space Flight Center, that it will release a new processor Intellectual Property (IP) core based on the SPARC instruction set architecture (ISA). The new LEON5 processor IP core, which succeeds the previous LEON4 processor, will be made available on 25 December for download into Xilinx’ Kintex UltraSCALE FPGAs.

Read the full press release.  

Vacancy Notice

We're looking for a Computer Architect and an ASIC/FPGA Engineer to join our team ...read more

Get updates via e-mail

Please use this form to sign up for the Cobham Gaisler Newsletter.

 More news...