Cobham Gaisler AB provides IP cores and supporting development tools for embedded processors based on the SPARC architecture. We specialize in digital hardware design for both commercial and aerospace applications

News and Events

Latest Releases

LEON/GRLIB bitstreams for RTG4
GRLIB IP Library 2019.4-b4246
GR712RC user's manual 2.12
GR712RC data sheet 2.4
GR712RC-BOARD document 0.13 GR740 user's manual 2.3
GR716 data sheet 1.31
GR718B user's manual 3.3
LEON3FT-RTAX document 1.9
RT-SPW-ROUTER document 1.2

 GRMON3 Debug Monitor 3.2.1
GRMON2 Debug Monitor 2.0.98
TSIM2 LEON/ERC32 Simulator 2.0.65
GRSIM LEON MP Simulator 1.1.56
BCC Bare-C Compiler 2.1.1
RCC RTEMS Compiler 1.2.23, 1.3-rc7
VxWorks 7 support for LEON
VxWorks 6.9 support for LEON

 

 

See the LEON5 and NOEL-V video clip

The Gothenburg Symphony Orchestra has produced our video clip promoting the new LEON5 and NOEL-V processor IP cores that will be released on 25 December for  download into Xilinx’ Kintex UltraSCALE FPGAs. The original music score has been composed by Hans Ek who has also conducted the Gothenburg Symphony Orchestra when it was performed  as part of Kosmische Musik at the Gothenburg Concert Hall on 27 October 2018, 

 

Cobham Releases RISC-V Processor IP Core

Cobham Gaisler has announced  at the RISC-V Summit in San Jose, California, that it will release a new line of processor Intellectual Property (IP) cores that implements the RISC-V instruction set architecture (ISA). The NOEL-V processor IP core, the first product in the family, will be made available on 25 December for download into Xilinx’ Kintex UltraSCALE FPGAs.

Read the full press release.  

 

Cobham Releases LEON5 Processor IP Core

Cobham Gaisler has announced at the 12th Annual Workshop on Spacecraft Flight Software, at NASA Marshall Space Flight Center, that it will release a new processor Intellectual Property (IP) core based on the SPARC instruction set architecture (ISA). The new LEON5 processor IP core, which succeeds the previous LEON4 processor, will be made available on 25 December for download into Xilinx’ Kintex UltraSCALE FPGAs.

Read the full press release.  

 

 

Lift off: De-RISC to create first RISC-V, fully European platform for space

Launched on 1 October 2019, the European Innovation Action De-RISC is preparing a full hardware-software platform based on RISC-V for the space and aviation market.Combining a multicore system-on-chip by leading space solutions provider Cobham Gaisler with fentISS’ space-qualified XtratuM hypervisor, De-RISC will create a market-ready platform to power future space and aeronautical applications with made-in-Europe technology.

Read the full press release. 

 

Press releasee

ESA Supports Development of Cobham’s GR740 Microprocessor in Organic Package

Cobham Gaisler has announced that they have successfully negotiated a contract with the European Space Agency (ESA) leading to the development and validation of its GR740 Quad-Core LEON4FT Microprocessor in an Organic Package. Cobham Gaisler will lead this joint development effort with semiconductor supplier STMicroelectronics (NYSE: STM) and Synergie Cad PSC (France). This development will help meet market demand for high reliability, low cost components for large constellations and new space applications. 
Read the full press release. 

Cobham Awarded Contract from European Space Agency for GR740 SBC Reference Design

Cobham Gaisler has announced it is leading a consortium for a new development contract from the European Space Agency (ESA). Cobham Gaisler and RUAG Space, both located in Gothenburg, Sweden, with specification input from Airbus Defense and Space, Thales Alenia Space and OHB Systems, will together design a reference design and basic software for a single board computer (SBC) based on the GR740 Quad-Core LEON4FT Microprocessor. 
Read the full press release.

DLR Utilizes Cobham’s Dual-Core Processors in Eu:CROPIS Satellite and Next Generation Payload Demonstrator

Cobham Gaisler and DLR (German Aerospace Center) announced that Cobham’s GR712RC Dual-Core LEON3FT Processor has been successfully used to control the Eu:CROPIS (Euglena Combined Regenerative Organic Food Production in Space) satellite for more than 350 days in orbit. In addition, the GR712RC is also used in DLR’s SCalable On-BoaRd Computing Experiment (SCORE) payload.
Read the full press release.

GR740 USer Day

GR740 User Day at ESTEC

The GR740 User Day will take place in the Erasmus Auditorium at ESTEC, Noordwijk, and is free of charge and will be open to the public.

The presentations are available on-line. 

ESA contract for High-Performance Compute Board

A development contract has been awarded from ESA to a Cobham Gaisler lead consortium that will result in the design of an accelerator board suitable for Computer Vision (CV) and Artificial Intelligence (AI) applications for in-orbit space use. 
Read the full press release.

     

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 SBS3740

DDC's New 3U SBC Incorporates Cobham Processor Technology

Data Device Corporation (DDC) and Cobham Gaisler jointly announced at the RADECS (RADiation Effects on Components and Systems) Conference that the radiation-hardened GR740 Quad-Core LEON4FT (Fault-Tolerant) Processor device will be used in DDC’s latest Rad-Hard Single Board Computer (SBC), the SCS3740. Read the full press release.

 Rymdveckan

 Cobham Gaisler will participate in Rymdveckan, or "Space Week" that will be held in Gothenburg, Sweden, between 14th and 22nd of September. Read the full details of our engagement.

VESTA-1 

Cobham Processor Technology Powers Commercial NanoSatellite

Cobham Gaisler’s LEON3FT processor technology is used on the VESTA-1 nanosatellite developed and operated by Surrey Satellite Technology Ltd (SSTL). SSTL has recently confirmed the successful commissioning and operation of VESTA-1, a 3U nanosatellite technology demonstration mission that will test a new two-way VHF Data Exchange System (VDES) payload developed by Honeywell for the ExactEARTH advanced maritime satellite constellation. Read the full press release. 

RISC-V

Cobham Joins RISC-V Foundation

Cobham Gaisler has announced that is has recently been accepted as a Gold-Level Member of the RISC-V Foundation and intends to release products based on the RISC-V ISA in parallel with the further development of its LEON SPARC processor based products. The initial RISC-V product will be a RV64GC compliant processor Intellectual Property (IP) core written in VHDL. Read the full press release.

 

GRMON 3.0 release now available 

Cobham Gaisler released in March 2018 the new GRMON3 debug monitor. In addition to the features found in previous GRMON versions a new graphical user interface greatly extends the traditional monitoring and control capabilities. Please see the GRMON3 product page for more information. 

Vacancy Notice

We're looking for a Computer Architect and an ASIC/FPGA Engineer to join our team ...read more

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