|
Exploring Register File and Memory Organization in ASIP Synthesis
|
Written by Sandi Habinc |
11781 |
|
Comparison of the Performance of Microprocessors for Space-based Navigation Applications
|
|
12553 |
|
Successful Use of an Open Source Processor in a Commercial ASIC
|
|
11538 |
|
Liquid Architecture
|
Written by Administrator |
11475 |
|
Architecture, Memory and Interface Technology Integration of an Industrial/Academic Configurable SoC
|
Written by Administrator |
12195 |
|
Embedded 32-Bit RISC IP Cores and OPEX JavaBytecode Folding
|
Written by Administrator |
11895 |
|
Mixed Static/Dynamic Profiling for Dictionary Based Code Compression
|
Written by Administrator |
10905 |
|
An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined
|
Written by Administrator |
10839 |
|
Hardware/Software Co-Training
|
Written by Administrator |
12492 |
|
Reconfigurable Hardware in Wearable Computing Nodes
|
Written by Administrator |
11553 |
|
Development cost and size estimation starting from high-level specifications
|
Written by Administrator |
12835 |
|
Design Flow for HW / SW Acceleration Transparency in the ThumbPod Secure Embedded System
|
Written by Administrator |
14593 |
|
Low power error resilient encoding for on-chip data buses
|
Written by Administrator |
11219 |
|
Analysis of SEU effects in a pipelined processor
|
Written by Administrator |
13194 |
|
Hardware/Software Co-testing of Embedded Memories in Complex SOCs
|
Written by Administrator |
11775 |
|
Safety-Critical Architectures for Automotive Applications
|
Written by Administrator |
12067 |
|
A Pipelined SoPC Architecture for 2.5 Gbps Network Processing
|
Written by Administrator |
11997 |
|
Experiences Designing a System-on-a-Chip for Small Satellite Data Processing and Control
|
Written by Administrator |
12321 |