Cobham Gaisler AB provides IP cores and supporting development tools for embedded processors based on the SPARC architecture. We specialize in digital hardware design for both commercial and aerospace applications
GRSPW2 SpaceWire Link
The GRSPW2 core implements a SpaceWire link controller with RMAP support and AMBA host interface. The core complies to the SpaceWire standard (ECSS-E-ST-50-12C) with the protocol identification extension (ECSS-E-ST-50-51C) and RMAP protocol (ECSS-E-ST-50-52C). Receive and transmit data is autonomously transferred between the SpaceWire Codec and the AMBA AHB bus using DMA transfers. Through the use of receive and transmit descriptors, multiple SpaceWire packets can be received and transmitted without CPU involvement. The GRSPW2 control registers are accessed through an APB interface. For critical space applications, a fault-tolerant (FT) version of GRSPW2 is available with full SEU protection of all RAM blocks.
New features
GRSPW2 is the successor to the GRSPW. It is based on the old core and contains all of its functionality and features while also adding new ones. The major differences are shown in the table below.
| Feature | GRSPW | GRSPW2 |
| RMAP | Draft C | Draft F |
| Clock factor | 4 | 8 |
| DMA channels | 1 | 4 |
| Timers | System clock | SpaceWire clock |
| Addressing | Single address | Multiple addresses and ranges |
- GRPSW2 implements RMAP error code 12 (Invalid destination logical address) which is the only part missing in GRSPW (not making it draft F compliant).
- The clock factor is the largest difference in clock frequency between the AHB clock and the SpaceWire clock. GRSPW2 has doubled this factor.
- Up to four DMA channels can be implemented in GRSPW2 while the old core only supports one.
- The GRSPW required configuration of the disconnect and 6.4 us timers since they used the system clock. The new core uses the SpaceWire transmit clock which makes that extra configuration step unnecessary.
- GRSPW2 supports separate logical addresses for each DMA channel with a corresponding mask that can be used to disable individual bits during address comparison effectively creating address ranges.
Area and timing
The GRSPW2 increased speed comes with an area penalty compared to the GRSPW. The table below shows the approximate Cell/LUT count and frequency for eight different GRSPW2 configurations on Actel RTAX, Xilinx Spartan3, Xilinx Virtex2 and ASIC technologies.
(Cells / RAM blocks / AHB MHz / SPW Rx Mbps)
| Core configuration | RTAX | RTProASIC3 | Virtex5 | ASIC | |
| GRSPW2 | 4,200 / 3 / 60 / 250 | 5,800 / 5 / 45 / 180 | 1,800 / 3 / 130 / 400 | 15,000 gates | |
| GRSPW2 + RMAP(1) | 5,800 / 4 / 60 / 250 | 8,500 / 6 / 45 / 180 | 2,700 / 4 / 130 / 400 | 20,000 gates | |
| GRSPW2 + 2P(2) | 4,400 / 3 / 60 / 250 | 6,100 / 5 / 45 / 180 | 1,800 / 3 / 130 / 400 | 15,000 gates | |
| GRSPW2+4DMA(3) | 5,400 / 3 / 60 / 250 | 7,400 / 5 / 45 / 180 | 2,200 / 3 / 130 / 400 | 19,000 gates | |
| GRSPW2+ RMAP + 2P + 4DMA | 7,400 / 4 / 60 / 250 | 10,200 / 6 / 45 / 180 | 3,300 / 4 / 130 / 400 | 26,000 gates | |
| GRSPW2-FT(4) | 4,300 / 5 / 60 / 250 | 6,000 / 10 / 45 / 180 | 1,800 / 5 / 130 / 400 | 15,000 gates | |
| GRSPW2-FT + RMAP | 5,900 / 6 / 60 / 250 | 8,500 / 12 / 45 / 180 | 2,800 / 6 / 130 / 400 | 21,000 gates | |
| GRSPW2-FT + RMAP + 2P + 4DMA | 7,200 / 6 / 60 / 250 | 10,400 / 12 / 45 / 180 | 3,400 / 6 / 130 / 400 | 26,000 gates | |
| (1) Includes the RMAP command handler (2) Dual SpaceWire ports. One is available in the standard configuration |
(3) 4 DMA channels. One is available in the standard configuration (4) Fault tolerant version |
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Features
- Full implementation of SpacewWire standard
- Protocol ID extension ECSS-E-50-11
- Optional RMAP protocol ECSS-E-50-11
- AMBA AHB back-end with DMA
- Descriptor-based autonomous multi-packet transfer
- Low area and high frequency
- SEU protection fault-tolerance
- Portable
Benefits
- Tested and verified against several other SpaceWire cores
- Low area and high frequency
- Easily portable between FPGA and ASIC
- Low-cost project license
- SEU protection of all RAM blocks
Deliverables
- FPGA/ASIC netlist
- Stand-alone testbench
- Optional plug and play interface for GRLIB IP library
- User's manual
- Driver for RTEMS and VxWorks