Cobham Gaisler AB provides IP cores and supporting development tools for embedded processors based on the SPARC architecture. We specialize in digital hardware design for both commercial and aerospace applications

TSIM3 LEON3 beta

TSIM3 LEON3 beta release simulates the GR712RC LEON3FT dual-core chip as well as GR716 LEON3FT, UT700, UT699E, UT699 and a generic configurable LEON3.

The TSIM3 LEON3 beta can be evaluated with a TSIM2 LEON3 license with active support and maintenance or a GRSIM license. Contact This email address is being protected from spambots. You need JavaScript enabled to view it. for download credentials.

TSIM3 LEON3 beta introduces new functionality such as:

  • High precision multi-core model for GR712RC with bus contention and inter-processor effects modelled on a per instruction level
  • Improved SDRAM model
  • Tcl frontend with tab completion for both better automation and interactive use
  • GDB 8.2 support
  • More detailed built-in help for both commands and start options
  • New info reg command giving detailed device register information down to individual register fields
  • More detailed instruction tracing and new bus tracing

All this while still maintaining functionality and the accuracy profile of TSIM2 allowing efficient SW V&V development. As this is a beta release, not everything that TSIM3 will support is in place. Additional devices and some missing features of simulated devices will be added in the future. Please check this page again for future updates.

TSIM is an instruction-level simulator capable of emulating LEON-based computer systems. TSIM provides several unique features:

  • Emulation of LEON3 processors, including multi core support
  • FPU and MMU emulation
  • Standalone operation with scriptable and tab completing Tcl command line
  • Source level debugging via remote connection from GNU Debugger (GDB)
  • Provided as a library to be included in larger simulator frameworks (not supported in this beta release)
  • 64-bit time for practically unlimited simulation periods
  • Detailed instruction traces and AMBA bus traces
  • Memory emulation, including SDRAM, SRAM, PROM and caches.
  • Loadable modules to include user-defined device models
  • Non-intrusive execution time profiling
  • Non-intrusive code coverage monitoring
  • Stack backtrace with symbolic information
  • Check-pointing capability to save and restore complete simulator state (not supported in this beta release)
  • Unlimited number of breakpoints and watchpoints
  • Emulation of GR712RC (both processors emulated), GR716, UT699, UT699E, UT700

Two host platforms are supported: Linux and Windows 7 and 10.

Usage

TSIM can be run in stand-alone mode, or connected through a network socket to the GNU Debugger (GDB). In stand-alone mode, a variety of debugging commands are available to allow manipulation of memory contents and registers, breakpoint/watchpoint insertion, performance measurements, instruction traces and bus traces. Connected to (supported versions of) GDB, TSIM acts as a remote target and supports GDB debug requests. The communication between GDB and TSIM is performed using the GDB extended-remote protocol. Third-party debuggers supporting this protocol can be used.

The screenshot shows Eclipse connected to TSIM via GDB (click on image for a larger view).

Timing

The simulator time is maintained and incremented according the IU and FPU instruction timing. The parallel execution between the IU and FPU is modelled, as well as stalls due to operand dependencies. Instruction timing has been modelled after the real devices. Integer instructions have a higher accuracy than floating-point instructions due to the somewhat unpredictable operand-dependent timing of the FPU. Typical usage patterns have higher accuracy than atypical ones. The simulator time is maintained using 64-bit values providing virtually unlimited simulation time.

Device emulation

To simplify emulation of LEON3 devices, TSIM emulates on-chip peripherals and I/O cores in the following devices:

  • GR712RC: SpaceWire, CAN_OC, GPIO, FTMCTRL, SPI, Ethernet, GPTIMER, GRTIMER, UART etc.
  • GR716: SpaceWire, GRCAN, GPIO, FTMCTRL, Boot ROM, SPI, SPIM, GPTIMER, UART, DAC etc.
  • UT700: SpaceWire, PCI, Ethernet, CAN_OC, GPIO, SPI
  • UT699/E: SpaceWire, PCI, Ethernet, CAN_OC, GPIO

AHB and I/O emulation

TSIM has the capability to be extended with user-defined modules. This can be used to add simulation models of AHB and I/O devices as well as models connected to interfaces simulated by TSIM, such as GPIO and SPI. Such modules are loaded by TSIM at run-time. The modules has access to the simulator event queue, interrupts and other internal data structures, allowing for accurate emulation.  Modules are typically written in C, and can use any features of the host operating system. This provides high simulation performance and capability to communicate with any other framework (e.g. such as EUROSIM or SIMSAT).

Profiling

The TSIM profiling function calculates the amount of execution time spent in and under each subroutine of the simulated program. The profiling is non-intrusive. The Profiling does not have any affect on the execution in terms of simulated time and no changes needs to be done to the instrumented code. Twith both single he profiling information is printed as a list sorted on highest execution time ratio:

tsim> load dhrystone.elf

...
tsim> profile enable
  profiling enabled, sample period 1000
tsim> run
...
tsim> profile

  Merged profile for all started CPUs:

  function      ratio(%)
  --------      --------
  __bcc_crt0       99.99
  main             99.79
  Func_2           29.22
  strcmp           25.64
  memcpy           17.09
  Proc_8            8.34
  Func_1            4.77
  Proc_7            4.37
  Proc_6            1.78
tsim>

Code coverage monitoring

The TSIM code coverage support will monitor internally emulated memory. Default coverage is to combine the data from all CPUs, but it can be monitored indivually per CPU at the cost of larger memory usage. When coverage is enabled, TSIM registers whether a memory location has been read, written or executed. The coverage information can be displayed on the TSIM console or dumped to a file for batch post processing. When coverage is enabled, the simulation performance is decreased compared running TSIM with coverage disabled.

tsim> coverage enable 

  coverage enabled:
  0x00000000 - 0x00200000  : ROM
  0x40000000 - 0x40400000  : SRAM
  0x60000000 - 0x62000000  : SDRAM
tsim> coverage print strcmp
  40004ed4 :  1  1 11  0  1  1  1 11  0  1  1  1  1  1  1  1
  40004f14 :  9  1  0  0  1  1  1 11  0  1  1  1  1 19  1  1
  40004f54 :  1 11  1  1  1  9  1  0  0  1  1 19  1  1  1  1
  40004f94 :  1  9  1  0  0  0  0  1  1  1  0  0  1  9  1  0
  40004fd4 :  0  0  0  0  0  0  0  0  0  0  0  0  1  1  1  1
  40005014 :  1  1  1  1  9  1  0  0  0  0  0  0  0  0  0  0
  40005054 :  0  0  0  0  1  1 19  1  1  1  0  0  0  0  0  0
  40005094 :  0  0  0  0  0  0  0  0  0  0  4  0  0  0  0  0
  400050d4 :  0  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
  40005114 :  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
  40005154 :  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
  40005194 :  4  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
  400051d4 :  0  0  0  0  0  0  0  1  1  1  1  1  1  1  1  1
  40005214 :  1 11  1  1  1 11  1  1  1  1 11  0  1  1  1 11
  40005254 :  1  1  1 11  0  1  1  1 19  1  1  1  1  1  1  1
  40005294 : 11  1  1  1 19  1  1 11  0  1  1  1  1  1  1  1

Performance

A collection of performance statistics are automatically calculated and can be displayed with the 'perf' command:

tsim> perf
  Merged performance statistics for all started CPUs:
   Cycles       : 505070460
   Instructions : 347034919
   Overall CPI  :      1.46
   CPU performance (50.0 MHz)  :  34.36 MOPS (34.36 MIPS, 0.00 MFLOPS)
   Cache hit rate              :  100.0 % (inst: 100.0, data: 100.0)
   Simulated time              :  10.10 s
   Processor utilisation       : 100.00 %
 
  Performance of the simulator:
   Real-time performance       :  98.57 %
   Simulator performance       :  33.86 MIPS
   Used time (sys + user)      :  10.25 s
Host support

TSIM is available for Linux and Windows 7 and 10.

Users and projects

More than 500 commercial TSIM licenses have been sold and are being used in various LEON and ERC32 projects. Many more copies of the evaluation version of TSIM are used by individuals and universities. TSIM is the market leader for LEON and ERC32 simulation, and used in major space projects such as Cryosat, ATV, Beagle-2, Ariane-5, GOCE, Herschel/Planck, PROBA-2 and many others.

Download

To download TSIM or the user's manual, please proceed to the download page.with both single