The NOEL-V is a synthesizable VHDL model of a processor that implements the RISC-V architecture. The processor is the first released model in our RISC-V line of processors that complement the LEON line of processors.
The NOEL-V can be implemented as a dual-issue processor, allowing up to two instructions per cycle to be executed in parallel. To support the instruction issue rate of the pipeline, the NOEL-V has advanced branch prediction capabilities. The cache controller of the NOEL-V supports a store buffer FIFO with one cycle per store sustained throughput, and wide AHB slave support to enable fast stores and fast cache refill.
The NOEL-V is interfaced using the AMBA 2.0 AHB bus (subsystem with Level-2 cache and AXI4 backend is also available) and supports the IP core plug&play method provided in the our IP library (GRLIB). The processor can be efficiently implemented on FPGA and ASIC technologies and uses standard synchronous memory cells for caches and register file.
The NOEL-V processor has the following features:
The NOEL-V processor can be synthesized with common synthesis tools such as Xilinx Vivado, Synplify, and Synopsys DC. The processor model is highly portable between different implementation technologies.
The NOEL-V processor implements the RISC-V ISA which means that compilers and kernels for RISC-V can be used with NOEL-V (kernels will need a NOEL-V BSP). To simplify software development, we provide several prebuilt toolchains. Currently, the NOEL-V processor is supported by pre-built RTEMS and Linux toolchains. We provide VxWorks 7 BSP for NOEL-V under commercial license. Over time, the NOEL-V software support will be extended to the same level of support that exists for the LEON line of processors.
The GRMON monitor interfaces to the NOEL-V on-chip debug support unit, implementing a large range of debug functions including GDB support for source level debugging.
The NOEL-V processor core is available as part of a subsystem that also contains system peripherals. The subsystem can be configured to use the processor configurations listed in the table below. The configurations listed below are the ones recommended by us since they are covered by regression tests. Software toolchains provided by us are developed and built considering the same configurations. It is also possible to tailor additional configuration settings to create custom processor configurations by editing the VHDL generic (configuration parameter) assignments in the subsystem.
|TIN32||RV32IM||single issue||no||no||no||no||Tiny configuration.|
|MIN32||RV32IMAC||single issue||yes||no||yes||no||Minimal 32-bit configuration|
|MIN64||RV64IMAC||single issue||yes||no||yes||no||Minimal 64-bit configuration|
|GPP32||RV32GCH||single or dual issue||yes||yes||yes||GRFPU or NanoFPU||General purpose 32-bit configuration|
|GPP64||RV64GCH||single or dual issue||yes||yes||yes||GRFPU or NanoFPU||General purpose 64-bit configuration|
|HPP32||RV32GCH||dual issue||yes||yes||yes||GRFPU or NanoFPU||High-performance 32-bit configuration|
|HPP64||RV64GCH||dual issue||yes||yes||yes||GRFPU or NanoFPU||High-performance 64-bit configuration|
Note: Configurations were updated 2021-Mar-04
Note*: Key for ISA column:
The current release of NOEL-V has the following limitations:
Note: The standard configurations may be extended when additional extensions are supported by NOEL-V. For example, the Zbb extension may become part of the standard configurations in the future.
NOEL-V is part of the GRLIB IP Library from release 2020.2 There are also pre-built FPGA development board bitstreams available. Additional features for the NOEL-V processor will become available as part of milestone releases. The table below shows the planned milestones. Please note that the future milestone features and dates are tentative.
|v0||First RV64IMC release. Available as NOEL-XCKU example design.||2019-Dec|
|v1 - v2||
Source release to first adopters, with the following features:
The v3 release is the first generally available source release.
Allows to create SoCs equivalent to LEON3/4/5 systems in terms of functionality:
The v4 release introduces configurations that are suitable for more FPGA implementations
Support for TIN32, MIN32, GPP32, GPP64, HPP32 configurations.
The v5 release adds fault-tolerance features and performance improvements:
|v6 - ..||
Features under consideration for the v6 release and beyond include:
The NOEL-V is part of our free open source GRLIB IP Library (the pipelined GRFPU5 is a commercial-only offering and will not be included in the free open source distribution). NOEL-V is also available under a low-cost commercial license, allowing it to be used in any commercial application. The commercial NOEL-V license includes:
FPGA programming files are also available for the following FPGA boards:
We maintain a Discourse forum for those interested in the open source company's processor products.