Introduction
The NOEL-V is a synthesizable VHDL model of a processor that implements the RISC-V architecture. The processor is the first released model in our RISC-V line of processors that complement the LEON line of processors.
The NOEL-V can be implemented as a dual-issue processor, allowing up to two instructions per cycle to be executed in parallel. To support the instruction issue rate of the pipeline, the NOEL-V has advanced branch prediction capabilities. The cache controller of the NOEL-V supports a store buffer FIFO with one cycle per store sustained throughput, and wide AHB slave support to enable fast stores and fast cache refill.
The NOEL-V is interfaced using the AMBA 2.0 AHB bus (subsystem with Level-2 cache and AXI4 backend is also available) and supports the IP core plug&play method provided in the our IP library (GRLIB). The processor can be efficiently implemented on FPGA and ASIC technologies and uses standard synchronous memory cells for caches and register file.
The NOEL-V processor has the following features:
The NOEL-V processor can be synthesized with common synthesis tools such as Xilinx Vivado, Synplify, and Synopsys DC. The processor model is highly portable between different implementation technologies.
Software development
The NOEL-V processor implements the RISC-V ISA which means that compilers and kernels for RISC-V can be used with NOEL-V (kernels will need a NOEL-V BSP). To simplify software development, we provide several prebuilt toolchains. Currently, the NOEL-V processor is supported by pre-built RTEMS and Linux toolchains. We provide VxWorks 7 BSP for NOEL-V under commercial license. Over time, the NOEL-V software support will be extended to the same level of support that exists for the LEON line of processors.
The GRMON monitor interfaces to the NOEL-V on-chip debug support unit, implementing a large range of debug functions including GDB support for source level debugging.
Configurations
The NOEL-V processor core is available as part of a subsystem that also contains system peripherals. The subsystem can be configured to use the processor configurations listed in the table below. The configurations listed below are the ones recommended by us since they are covered by regression tests. Software toolchains provided by us are developed and built considering the same configurations. It is also possible to tailor additional configuration settings to create custom processor configurations by editing the VHDL generic (configuration parameter) assignments in the subsystem
Configuration |
Target |
Architecture |
Pipeline |
RISC-V extensions |
MMU |
PMP |
Privilege modes |
Example SW |
HP |
High-performance processing |
32 or 64 bits |
Dual issue |
IMAFDB*CH |
Yes |
Yes |
Supervisor, User and Machine + Virtualization |
Hypervisor, Linux, VxWorks |
GP |
General purpose processing |
32 or 64 bits |
Dual or single issue |
IMAFDB*CH |
Yes |
Yes |
Supervisor, User and Machine + Virtualization |
Hypervisor, Linux, VxWorks |
GP-lite |
General purpose processing Area optimized |
32 or 64 bits |
Dual or single issue |
IMAFDB*C |
Yes |
No |
Supervisor, User and Machine |
Linux, VxWorks |
MC |
Controller applications |
32 or 64 bits |
Single issue |
IMAFDB*C |
No |
Yes |
User and Machine |
RTEMS |
MC-lite |
Controller applications Area Optimized |
32 or 64 bits |
Single issue |
IMA |
No |
No |
User and Machine |
RTEMS |
*only parts of the B extensions may be enabled for this configuration. Check GRIP.pdf for more information
Note: Configurations were updated 2022-August-01
Note*: Key for ISA column:
Note: The standard configurations may be extended when additional extensions are supported by NOEL-V.
Availability and licensing
The NOEL-V is part of our free open source GRLIB IP Library (the pipelined GRFPUnv is a commercial-only offering and not included in the free open source distribution). NOEL-V is also available under a low-cost commercial license, allowing it to be used in any commercial application. Please see the GRLIB IP Core User's Manual - Processor license overview for license types.
Demonstration systems and documentation
Item | File |
NOEL-V IP core documentation | GRLIB IP Core User's Manual, see NOEL-V Subsystem |
NOEL-V Product Brief | NOEL-V Product Brief.pdf (August 2022) |
The free open source version of GRLIB is available here: GRLIB IP Library
FPGA programming files are available for the following FPGA boards:
Development roadmap
NOEL-V is part of the GRLIB IP Library from release 2020.2 There are also pre-built FPGA development board bitstreams available. Additional features for the NOEL-V processor will become available as part of milestone releases. The table below shows the planned milestones. Please note that the future milestone features and dates are tentative.
Milestone | Description | Date |
---|---|---|
v7 |
Features in the v7 release include:
|
2022-Q2 |
v8 |
Features planned for the v8 release include:
|
2022-Q4 |
v9 | Features planned for the v9 release include:
|
2023-Q1 |
v10 - .. |
Features in the roadmap for release include:
|
Community
We maintain a Discourse forum for those interested in the open source company's processor products.