Cobham Gaisler AB provides IP cores and supporting development tools for embedded processors based on the SPARC architecture. We specialize in digital hardware design for both commercial and aerospace applications

NOEL-V Processor

IntroductionNOEL-V

The NOEL-V is a synthesizable VHDL model of a 64-bit processor that implements the RISC-V architecture. The processor is the first released model in Cobham Gaisler's RiSC-V line of processors that complement the LEON line of processors.

The NOEL-V is dual-issue, allowing up to two instructions per cycle to be executed in parallel. To support the instruction issue rate of the pipeline, the NOEL-V has advanced branch prediction capabilities. The cache controller of the NOEL-V supports a store buffer FIFO with one cycle per store sustained throughput, and wide AHB slave support to enable fast stores and fast cache refill.

The NOEL-V is interfaced using the AMBA 2.0 AHB bus (subsystem with Level-2 cache and AXI4 backend is also available) and supports the IP core plug&play method provided in the Cobham Gaisler IP library (GRLIB). The processor can be efficiently implemented on FPGA and ASIC technologies and uses standard synchronous memory cells for caches and register file.

The NOEL-V processor has the following features:

  • RISC-V RV64GC
    • 64-bit architecture
    • Hardware multiply and divide units
    • Compressed (16 bit) instruction support
    • Atomic instruction extension
    • 32/64 bit floating point extensions using non-pipelined area efficient FPU or high-performance fully pipelined IEEE-754 FPU
    • Machine, supervisor and user mode. RISC-V standard MMU with configurable TLB.
    • User level interrupts
  • RISC-V standard PLIC
  • RISC-V standard PMP (physical memory protection)
  • RISC-V standard external debug support
  • Advanced 7-stage dual-issue in-order pipeline
  • Dynamic branch prediction, branch target buffer and return address stack
  • Four full ALUs, two of them late in the pipeline to reduce stalls
  • Separate instruction and data L1 cache (Harvard architecture) with snooping
  • Optional L2 cache: 256-bit internal, 1-4 ways, 16 KiB - 8 MiB
  • Native AMBA 2.0 AHB bus interface, 32-, 64- or 128-bit wide.
    • Subsystem including processor and Level-2 cache with AXI4 backend also available.
  • Robust and fully synchronous single-edge clock design
  • Extensively configurable
  • Large range of software tools: compilers, kernels and debug monitors
  • High Performance: CoreMark*: 4.03 / 4.69** CoreMark/MHz
    *-march=rv64im -mabi=lp64 -O2 -funroll-all-loops -funswitch-loops -fgcse-after-reload -fpredictive-commoning -mtune=sifive-7-series
    -finline-functions -fipa-cp-clone -falign-functions=8 -falign-loops=8 -falign-jumps=8 --param max-inline-insns-auto=20 using GCC 9.2.0 under RTEMS 5
    ** Using "#define ee_u32 int32_t" in core_portme.h, as is common for 64 bit RISC-V.
Synthesis

The NOEL-V processor can be synthesized with common synthesis tools such as Xilinx Vivado, Synplify, and Synopsys DC. The processor model is highly portable between different implementation technologies.

Software development

The NOEL-V processor implements the RISC-V ISA which means that compilers and kernels for RISC-V can be used with NOEL-V (kernels will need a NOEL-V BSP). To simplify software development, Cobham Gaisler provides several toolchains. At the initial release, the NOEL-V processor will be supported by pre-built RTEMS toolchains. Over time, the NOEL-V software support will be extended to the same level of support that exists for the LEON line of processors

The GRMON monitor interfaces to the NOEL-V on-chip debug support unit, implementing a large range of debug functions including GDB support for source level debugging.

Availability

FPGA programming files with NOEL-V have been released on December 25 2019. The initial release contains an RV64IMC implementation, with AFD (ie GC) to be released during 2020.

Implementation of the N and H extensions have been prototyped and their inclusion is under evaluation.

The full source code will available in Cobham Gaisler's free open source GRLIB IP Library (the pipelined GRFPU5 is a commercial-only offering and will not be included in the free open source distribution). NOEL-V is also available under a low-cost commercial license, allowing it to be used in any commercial application.

Demonstration systems and documentation

NOEL-V documentation is available in the GRLIB IP Library User's Manual - NOEL-V subsystem.

FPGA programming files are also available, please see the NOEL-XCKU example design.