Introduction

The NOEL-V is a synthesizable VHDL model of a processor that implements the RISC-V architecture. The processor is the first released model in our RISC-V line of processors that complement the LEON line of processors.

The NOEL-V can be implemented as a dual-issue processor, allowing up to two instructions per cycle to be executed in parallel. To support the instruction issue rate of the pipeline, the NOEL-V has advanced branch prediction capabilities. The cache controller of the NOEL-V supports a store buffer FIFO with one cycle per store sustained throughput, and wide AHB slave support to enable fast stores and fast cache refill.

The NOEL-V is interfaced using the AMBA 2.0 AHB bus (subsystem with Level-2 cache and AXI4 backend is also available) and supports the IP core plug&play method provided in the our IP library (GRLIB). The processor can be efficiently implemented on FPGA and ASIC technologies and uses standard synchronous memory cells for caches and register file.

The NOEL-V processor has the following features:

• RISC-V 32-bit and 64-bit architecture
• Hardware multiply and divide units
• Compressed (16 bit) instruction support
• Atomic instruction extension
• 32/64 bit floating point extensions using non-pipelined area efficient FPU or high-performance fully pipelined IEEE-754 FPU
• Machine, supervisor and user mode. RISC-V standard MMU with configurable TLB.
• User level interrupts
• RISC-V standard PLIC
• RISC-V standard PMP (physical memory protection)
• RISC-V standard external debug support
• Advanced dual-issue in-order pipeline
• Dynamic branch prediction, branch target buffer and return address stack
• Four full ALUs, two of them late in the pipeline to reduce stalls
• Separate instruction and data L1 cache (Harvard architecture) with snooping
• Optional L2 cache: 256-bit internal, 1-4 ways, 16 KiB - 8 MiB
• Native AMBA 2.0 AHB bus interface, 32-, 64- or 128-bit wide.
• Subsystem including processor and Level-2 cache with AXI4 backend also available.
• Robust and fully synchronous single-edge clock design
• Extensively configurable
• Large range of software tools: compilers, kernels and debug monitors
• High Performance*: CoreMark: 4.03** / 4.69*** CoreMark/MHz
  ^{*For HPP64 configuration. CoreMark score varies with processor configuration, microarchitectural changes, and toolchains. The CoreMark score is preliminary and will be updated for the v4 and v5 milestones.
  **-march=rv64im -mabi=lp64 -O2 -funroll-all-loops -funswitch-loops -fgcse-after-reload -fpredictive-commoning -mtune=sifive-7-series
  -finline-functions -fipa-cp-clone -falign-functions=8 -falign-loops=8 -falign-jumps=8 --param max-inline-insns-auto=20 using GCC 9.2.0 under RTEMS 5
  *** Using "#define ee_u32 int32_t" in core_portme.h, as is common for 64 bit RISC-V.}

Software development

The NOEL-V processor implements the RISC-V ISA which means that compilers and kernels for RISC-V can be used with NOEL-V (kernels will need a NOEL-V BSP). To simplify software development, we provide several prebuilt toolchains. Currently, the NOEL-V processor is supported by pre-built RTEMS and Linux toolchains. We provide VxWorks 7 BSP for NOEL-V under commercial license. Over time, the NOEL-V software support will be extended to the same level of support that exists for the LEON line of processors.

The GRMON monitor interfaces to the NOEL-V on-chip debug support unit, implementing a large range of debug functions including GDB support for source level debugging.

Configurations

The NOEL-V processor core is available as part of a subsystem that also contains system peripherals. The subsystem can be configured to use the processor configurations listed in the table below. The configurations listed below are the ones recommended by us since they are covered by regression tests. Software toolchains provided by us are developed and built considering the same configurations. It is also possible to tailor additional configuration settings to create custom processor configurations by editing the VHDL generic (configuration parameter) assignments in the subsystem.

Note: Configurations were updated 2021-Mar-04
Note*: Key for ISA column:

• RV32I - 32-bit Base Integer instructions
• RV64I - 64-bit Base Integer instructions
• M - Hardware support for multiply and division
• A - Atomics
• FD - Single/Double Floating Point
• G - short for IMAFD
• C - Compressed instructions
• H - Hardware hypervisor support

Note: The standard configurations may be extended when additional extensions are supported by NOEL-V.

Availability

NOEL-V is part of the GRLIB IP Library from release 2020.2 There are also pre-built FPGA development board bitstreams available. Additional features for the NOEL-V processor will become available as part of milestone releases. The table below shows the planned milestones. Please note that the future milestone features and dates are tentative.

The NOEL-V is part of our free open source GRLIB IP Library (the pipelined GRFPUnv is a commercial-only offering and will not be included in the free open source distribution). NOEL-V is also available under a low-cost commercial license, allowing it to be used in any commercial application. The commercial NOEL-V license includes:

• High-performance pipelined GRFPUnv floating-point unit
• The L2CACHE Level-2 cache controller
• GRIOMMU IO memory management unit
• Additional peripheral IP as described in the GRLIB IP Core User's Manual

Demonstration systems and documentation

GRLIB IP Library

NOEL-V documentation is available in the GRLIB IP Library User's Manual - NOEL-V subsystem.

FPGA programming files are also available for the following FPGA boards:

• Digilent Arty-A7: NOEL-ARTYA7 example designs
• Microsemi PolarFire Splash Kit: NOEL-PF example designs
• Xilinx KCU105: NOEL-XCKU example designs

Community

We maintain a Discourse forum for those interested in the open source company's processor products.

Documentation