FTADDR is a memory controller for DDR2 and DDR3 SDRAM memory devices. It uses a strong error correction code to achieve exceptional fault tolerance.
On the memory side, it presents a DFI interface for connection to an on-chip physical layer (PHY) that manages the low-level timing and data recovery and then provides the I/O buffers. Towards the system-on-chip, it presents the memory through an AMBA AHB slave interface.
Features
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![]() FTADDR can be synthesized with common commercial synthesis tools. The IP model is highly configurable and portable between different implementation technologies, for both FPGA and ASIC. For ASIC implementations, a DFI compliant PHY and SSTL IO buffers are also required |
Availability
FTADDR is available as a separate package or as an addition to commercial versions of the GRLIB VHDL library. Contact This email address is being protected from spambots. You need JavaScript enabled to view it. for licensing information.
Example designs for Xilinx and Altera FPGA evaluation boards are readily available.
Documentation
Document | File |
FTADDR IP User's Manual | GRLIB IP Core User's Manual, see FTADDR |