DDR2/DDR3/DDR4 Memory controller

On the memory side, the IP presents a DFI interface for connection to an on-chip physical layer (PHY) that manages the low-level timing and data recovery and then provides the I/O buffers. Towards the system-on-chip, it presents the memory through an AMBA AHB slave interface.

• 96-bit interface with dual x8 device correction capability
  
  • Ensures accurate data even in the event of one full device failure and random SEU-induced errors on other devices
• 80-bit interface with x8 device correction capability
• 72-bit interface with SECDEC (compatiblewith UT8SD4MQ2G72 18GB DDR4)
• TMR and 5MR (24-bit and 40-bit) for x8 devices

FTADDR can be synthesized with common commercial synthesis tools. The IP model is highly configurable and portable between different implementation technologies, for both FPGA and ASIC. For FPGA, specific imlementations are available for Xilinx Ultrascale and Altera UniPhy technologies. Implementation for Microchip PolarFire is on-going.

The IP core is available as a separate package or as an addition to commercial versions of the GRLIB VHDL library.

Contact sales@gaisler.com for licensing information.