LEON5 Processor


The LEON5 is a synthesizable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture. The model is highly configurable and suitable for system-on-chip (SOC) designs.

LEON5 provides backward compatibility for most software implementations that have targeted LEON3 and LEON4 processors. The LEON5 primarily targets high-end FPGA:s and deep-submicron ASIC technologies. For legacy and less performant technologies, the LEON3 processor is the recommended choice that continues to be maintained.

The processor pipeline design of the LEON5 is significantly enhanced compared to earlier LEON3 and LEON4 processors, and initial evaluations show that LEON5 can provide up to 85% faster execution for single-threaded integer benchmarks compared to LEON4. The main new feature of the LEON5 pipeline is the dual-issue functionality, allowing up to two instructions per cycle to be executed in parallel in the processor. To support the increased issue rate of the pipeline, the LEON5 has advanced branch prediction capabilities. The cache controller of the LEON5 supports a store buffer FIFO with one cycle per store sustained throughput, wide AHB slave support to enable fast stores and fast cache refill, as well as several other enhancements.

The LEON5 is interfaced using the AMBA 2.0 AHB bus (subsystem with Level-2 cache and AXI4 backend is also available) and supports the IP core plug&play method provided in the our IP library (GRLIB). The processor can be efficiently implemented on FPGA and ASIC technologies and uses standard synchronous memory cells for caches and register file. The processor supports the MUL and DIV instructions, an IEEE-754 floating-point unit (FPU) and Memory Management Unit (MMU). The cache system consists of separate I/D multi-set Level-1 (L1) caches with up to 4 ways per cache, and an optional Level-2 (L2) cache for increased performance in data intensive applications.

The LEON5 processor has the following features:

  • SPARC V8 instruction set with V8e extensions and compare-and-swap
  • Advanced dual-issue pipeline
  • Complex dynamic branch predictor and small branch target buffer
  • Addition of Late ALU to decrease pipeline stalls
  • 64-bit single-clock load/store operation
  • 64-bit 4-port register file
  • Hardware multiply and divide units
  • Hardware floating-point support
    • Non-pipelined area efficient FPU (NanoFPU) or High-performance, fully pipelined IEEE-754 FPU including hardware support for denormalized numbers (GRFPU5)
  • Separate instruction and data L1 cache (Harvard architecture) with snooping
  • Optional L2 cache: 256-bit internal, 1-4 ways, 16 Kbyte - 8 Mbyte
  • SPARC Reference MMU (SRMMU) with TLB
  • AMBA-2.0 AHB bus interface, 32-, 64- or 128-bit wide
    • Subsystem including processor and Level-2 cache with AXI4 backend also available
  • Advanced on-chip debug support with instruction and data trace buffer, and performance counter
  • Symmetric Multi-processor support (SMP)
  • Power-down mode and clock gating
  • Robust and fully synchronous single-edge clock design
  • Large range of software tools: compilers, kernels, simulators and debug monitors
  • High performance:
    • Dhrystone*: 3.23 DMIPS/MHz  (-O3, inlining allowed)
    • Coremark* : 4.52 CoreMark/MHz (-O3,-funroll-all-loops -finline-functions -finline-limit=1000)
      * All the results generated using BCC 2.0.7 toolchain

As with previous generation LEON processors, the LEON5 processor model is being continuously extended. Planned extensions for 2020 include more advanced version of LEON5 with virtualization features and higher performance bus interconnect


The LEON5 processor can be synthesized with common synthesis tools such as Xilinx Vivado, Synplify, and Synopsys DC. The processor model is highly portable between different implementation technologies.

Software development

Being SPARC V8 conformant, compilers and kernels for SPARC V8 can be used with LEON5 (kernels will need a LEON BSP). To simplify software development, We provide several toolchains and operating systems.

Debugging is generally done using the GDB debugger, and a graphical front-end such as DDD or Eclipse. The GRMON monitor interfaces to the LEON5 on-chip debug support unit (DSU), implementing a large range of debug functions. The LEON5 processor will also be supported by our TSIM3 simulator.

Software compatibility

LEON5 provides backward compatibility for software designed for LEON3 and LEON4 systems with the following exceptions:

  • LEON5 does not support the SPARC V8e multiply-and-accumulate (MAC) instructions
  • LEON5 does not support the LEON-REX instruction set
  • Software that depend on version field values to identify LEON3 and LEON4 processors will see a different version value for LEON5

When HW virtualization is implemented and enabled, these incompatibilities can be hidden by the hypervisor.


The LEON5 processor core is available as part of subsystems that also contain system peripherals. The subsystems can be used to select the processor configurations listed in the table below. The listed configurations are the ones recommended by us since they are covered by regression tests. Software toolchains provided by us are developed and built considering the same configurations. It is possible to tailor additional configuration settings to create custom processor configurations by editing the VHDL generic (configuration parameter) assignments in the subsystem.

Configuration name LEON5-ADV
Subsystem top-level leon5adv leon5sys leon5sys leon5sys
Subsystem top-level generics (parameters)
perfcfg 0 0 1 2
fpuconf 1 1 1 0
Internal configuration
Issue rate Dual Dual Dual Single
I-cache 4x4KiB 4x4KiB 4x4KiB 1x4KiB
D-Cache 4x4KiB 4x4KiB 4x4KiB 1x4KiB
TLB I+D 24+24 24+24 16+16 4+4
Bus data width 32 - 128* 32 - 128* 32 - 128* 32 - 128*
HW virt Yes No No No
L2 cache Yes (striped) No** No** No**
IOMMU Yes (striped) No** No** No**

* Wide interface compatible also with 32-bit AHB masters and slaves
** L2 cache/IOMMU can be added externally as separate cores

Availability and licensing

LEON5 is part of our free open source GRLIB IP Library (the pipelined GRFPU5 is a commercial-only offering and not included in the free open source distribution). A simpler non-pipelined FPU is included in all distributions to make hardware floating point always available with the LEON5. LEON5 is also available under a low-cost commercial license, allowing it to be used in any commercial application. Please see the GRLIB IP Core User's Manual - Processor license overview for license types.

Demonstration systems and documentation

Item File
LEON5 IP core documentation GRLIB IP Core User's Manual,  see LEON5 Subsystem
LEON5 Product Brief LEON5 Product Brief.pdf (November 2021)

The free open source version of GRLIB is available here: GRLIB IP Library

FPGA programming files are also available for the following FPGA boards:

Development roadmap

LEON5 is part of our GRLIB IP Library from version 2020.2. Pre-built bitstreams for FPGA development kits are also available. The table below shows milestones for the planned future extensions to the LEON5. Please note that the milestone features and dates are tentative.

Milestone Description Date
v0 First public bitstream release. Available as LEON-XCKU example design. 2019-Dec

Possible upgrade from LEON3/LEON4 for commercial customers. First public source release of LEON5 subsystem (GPL/COM):

  • Virtually indexed, physically-tagged caches
  • new ASIs
  • Cache line flush
  • Extended debugging support

Possible upgrade from LEON3/4FT for high-end rad-hard FPGA customers

First release of FT basic LEON5 subsystem for rad-hard FPGA.


(GRLIB 2020.4)


Possible upgrade from LEON3/4FT for rad-hard ASIC customers

First release of FT basic LEON5 subsystem for ASIC with rad-hard stdcells: Additional FT features, support for tightly coupled memory, and internal memory scrubber.


(GRLIB 2021.1)


For new customer ASIC designs. First release of advanced LEON5 subsystem for commercial, FT-FPGA and ASIC with RH stdcells: Including address-striped buses and IOMMU integration. Virtualization support.


First version of advanced LEON5 subsystem for ASIC without RH stdcells: Advanced hardening by design approach using functional redundancy.

Real time tracing extensions



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