Cobham Gaisler AB provides IP cores and supporting development tools for embedded processors based on the SPARC architecture. We specialize in digital hardware design for both commercial and aerospace applications

LEON5 Processor

IntroductionLEON5

The LEON5 is a synthesizable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture. The model is highly configurable and suitable for system-on-chip (SOC) designs.

LEON5 provides backward compatibility for most software implementations that have targeted LEON3 and LEON4 processors. The LEON5 primarily targets high-end FPGA:s and deep-submicron ASIC technologies. For legacy and less performant technologies, the LEON3 processor is the recommended choice that continues to be maintained.

The processor pipeline design of the LEON5 is significantly enhanced compared to earlier LEON3 and LEON4 processors, and initial evaluations show that LEON5 can provide up to 85% faster execution for single-threaded integer benchmarks compared to LEON4. The main new feature of the LEON5 pipeline is the dual-issue functionality, allowing up to two instructions per cycle to be executed in parallel in the processor. To support the increased issue rate of the pipeline, the LEON5 has advanced branch prediction capabilities. The cache controller of the LEON5 supports a store buffer FIFO with one cycle per store sustained throughput, wide AHB slave support to enable fast stores and fast cache refill, as well as several other enhancements.

The LEON5 is interfaced using the AMBA 2.0 AHB bus (subsystem with Level-2 cache and AXI4 backend is also available) and supports the IP core plug&play method provided in the Cobham Gaisler IP library (GRLIB). The processor can be efficiently implemented on FPGA and ASIC technologies and uses standard synchronous memory cells for caches and register file. The processor supports the MUL and DIV instructions, an IEEE-754 floating-point unit (FPU) and Memory Management Unit (MMU). The cache system consists of separate I/D multi-set Level-1 (L1) caches with up to 4 ways per cache, and an optional Level-2 (L2) cache for increased performance in data intensive applications.

The LEON5 processor has the following features:

  • SPARC V8 instruction set with V8e extensions and compare-and-swap
  • Advanced dual-issue pipeline
  • Complex dynamic branch predictor and small branch target buffer
  • Addition of Late ALU to decrease pipeline stalls
  • 64-bit single-clock load/store operation
  • 64-bit 4-port register file
  • Hardware multiply and divide units
  • Hardware floating-point support
    • Non-pipelined area efficient FPU (NanoFPU) or High-performance, fully pipelined IEEE-754 FPU including hardware support for denormalized numbers (GRFPU5)
  • Separate instruction and data L1 cache (Harvard architecture) with snooping
  • Optional L2 cache: 256-bit internal, 1-4 ways, 16 Kbyte - 8 Mbyte
  • SPARC Reference MMU (SRMMU) with TLB
  • AMBA-2.0 AHB bus interface, 32-, 64- or 128-bit wide
    • Subsystem including processor and Level-2 cache with AXI4 backend also available
  • Advanced on-chip debug support with instruction and data trace buffer, and performance counter
  • Symmetric Multi-processor support (SMP)
  • Power-down mode and clock gating
  • Robust and fully synchronous single-edge clock design
  • Large range of software tools: compilers, kernels, simulators and debug monitors
  • High performance:
    • Dhrystone*: 3.23 DMIPS/MHz  (-O3, inlining allowed)
    • Coremark* : 4.52 CoreMark/MHz (-O3,-funroll-all-loops -finline-functions -finline-limit=1000)
      * All the results generated using BCC 2.0.7 toolchain

As with previous generation LEON processors, the LEON5 processor model is being continuously extended. Planned extensions for 2020 include more advanced version of LEON5 with virtualization features and higher performance bus interconnect

Synthesis

The LEON5 processor can be synthesized with common synthesis tools such as Xilinx Vivado, Synplify, and Synopsys DC. The processor model is highly portable between different implementation technologies.

Software development

Being SPARC V8 conformant, compilers and kernels for SPARC V8 can be used with LEON5 (kernels will need a LEON BSP). To simplify software development, Cobham Gaisler provides several toolchains and operating systems.

Debugging is generally done using the GDB debugger, and a graphical front-end such as DDD or Eclipse. The GRMON monitor interfaces to the LEON5 on-chip debug support unit (DSU), implementing a large range of debug functions. The LEON5 processor will also be supported by Cobham Gaisler's TSIM3 simulator.

Software compatibility

LEON5 provides backward compatibility for software designed for LEON3 and LEON4 systems with the following exceptions:

  • LEON5 does not support the SPARC V8e multiply-and-accumulate (MAC) instructions
  • LEON5 does not support the LEON-REX instruction set
  • Software that depend on version field values to identify LEON3 and LEON4 processors will see a different version value for LEON5

When HW virtualization is implemented and enabled, these incompatibilities can be hidden by the hypervisor.

Configurations

The LEON5 processor core is available as part of a subsystem that also contains system peripherals. The subsystem today only allows one primary configuration (LEON5-standard) that provides the superscalar LEON5 processor core. To support resource constrained targets, the subsystem will in a future release also support reduced variant (LEON5-small configuration). The configurations enforced by the subsystem  are the ones recommended by Cobham Gaisler since they are covered by regression tests. Software toolchains provided by Cobham Gaisler are developed and built considering the same configurations. It is also possible to tailor additional configuration settings to create custom processor configurations by editing the VHDL generic (configuration parameter) assignments in the subsystem.

Availability

LEON5 is part of Cobham Gaisler's GRLIB IP Library from version 2020.2. Pre-built bitstreams for FPGA development kits are also available. The table below shows milestones for the planned future extensions to the LEON5. Please note that the milestone features and dates are tentative.

MilestoneDescriptionDate
v0 First public bitstream release. Available as LEON-XCKU example design. 2019-Dec
v1

Possible upgrade from LEON3/LEON4 for commercial customers. First public source release of LEON5 subsystem (GPL/COM):

  • Virtually indexed, physically-tagged caches
  • new ASIs
  • Cache line flush
  • Extended debugging support
2020-Jun
v2

Possible upgrade from LEON3/4FT for high-end rad-hard FPGA customers

First release of FT basic LEON5 subsystem for rad-hard FPGA.

2020-Nov
v3

Possible upgrade from LEON3/4FT for rad-hard ASIC customers

First release of FT basic LEON5 subsystem for ASIC with rad-hard stdcells: Additional FT features, support for tightly coupled memory, and internal memory scrubber.

2021-Jan
v4

For new customer ASIC designs. First release of advanced LEON5 subsystem for commercial, FT-FPGA and ASIC with RH stdcells: Including address-striped buses and IOMMU integration. Virtualization support.

2021
v5

First version of advanced LEON5 subsystem for ASIC without RH stdcells: Advanced hardening by design approach using functional redundancy.

2021


LEON5 is part of Cobham Gaisler's free open source GRLIB IP Library. The pipelined GRFPU5 is a commercial-only offering and is not included in the free open source distribution of GRLIB. A simpler non-pipelined FPU is included in all distributions to make hardware floating point always available with the LEON5.

LEON5 is also available under a low-cost commercial license, allowing it to be used in any commercial application. The commercial LEON5 license includes:

  • High-performance pipelined GRFPU5 floating-point unit with denormalized number support
  • The L2CACHE Level-2 cache controller
  • GRIOMMU IO memory management unit
  • Additional peripheral IP as described in the GRLIB IP Core User's Manual

Demonstration systems and documentation

GRLIB IP Library

LEON5 documentation is available in the GRLIB IP Library User's Manual - LEON5 subsystem.

FPGA programming files are also available, please see the LEON-XCKU example design.

Community

Cobham Gaisler AB maintains a Discourse forum for those interested in the open source company's processor products.