USB 2.0 Host Controller

grusbhc-hostThe USB 2.0 Host Controller provides a link between the AMBA on-chip bus and the Universal Serial Bus (USB). The host controller supports High-, Full- and Low-Speed USB traffic.

USB 2.0 High-Speed functionality is supplied by an enhanced host controller implementing the Enhanced Host Controller Interface (EHCI). Full- and Low-Speed functionality (USB 2.0 and USB 1.1) is supplied by one or more companion controllers implementing the Universal Host Controller Interface (UHCI). The Port Router supplies the dynamic connection between the host controllers and the USB transceivers. The figure below shows a typical USB 2.0 host system with an enhanced host controller and a companion controller.

The core can handle up to 15 downstream ports, where each port can handle all three USB speeds. Port routing within the core is highly configurable. The designer has choices ranging from handling Full/Low-Speed traffic with one companion controller per port, to having one companion controller handle all ports. The modularity of the core enables the designer to configure High- or Full/Low-Speed only products. Both controller types have support for big and little endian systems, with the option to adjust the register interfaces' byte order to fit the target platform.

The enhanced host controller has support for Asynchronous Park Mode to allow consecutive bulk transactions to the same endpoint and a NAK counter to limit unnecessary memory accesses. The universal host controller's interface has been extended to report over current conditions. The core supports UTMI+ 16-bit transceivers at 30 MHz and 8-bit transceivers at 60 MHz, and ULPI 8-bit transceivers at 60 MHz.

GRUSBHC User's Manual

USB 2.0 Host Controller Product Brief PDF


The host controller core is inherently portable and can be implemented on most FPGA and ASIC technologies. Both area and timing of the core depends strongly on the selected configuration, target technology and the used synthesis tool.


Estimation of the resource utilization for the GRUSBHC can be found here:

Excel sheet for SoC area estimation


The IP can be implemented in any ASIC or FPGA technology. For specific information related to Xilinx, Microchip, and Lattice FPGAs, please refer to our dedicated web pages:

- Specific support for Lattice FPGAs

- Specific support for Microchip FPGAs

- Specific support for Xilinx FPGAs