Cobham Gaisler AB provides IP cores and supporting development tools for embedded processors based on the SPARC architecture. We specialize in digital hardware design for both commercial and aerospace applications

GRSPW_CODEC SpaceWire Codec

GRSPW_CODEC - SpaceWire Encoder Decoder

The GRSPW_CODEC core implements a SpaceWire encoder decoder with a 9-bit wide FIFO host interface in each direction. The core complies to the SpaceWire standard (ECSS-E-ST-12C). Data is transmitted and received through 9-bit wide FIFOs with configurable depth. The core also provides an interface for transmitting and receiving Time-codes as well as configuring the link properties such as speed.

For critical space applications, a fault-tolerant (FT) version of GRSPW_CODEC is available with full SEU protection of all RAM blocks

GRSPW_CODEC User's Manual: Please contact Cobham Gaisler at This email address is being protected from spambots. You need JavaScript enabled to view it. to acquire the documentation

GRSPW Codec Block Diagram


GRSPW_CODEC is the same codec as in the GRSPW2 but with a different host interface. Instead of using the advanced AMBA -AHB DMA and RMAP target a simple 9-bit wide FIFO interface is used instead. The host interface consists of 9-bit wide data interfaces to the FIFOs in both directions with accompanying read/write, full/character available and almost full/empty signals. The FIFOs can be configured from 16 to 2048 characters depth. Time-code transmission and reception is also supported using tickin/tickout and 8-bit timein/timeout signals.

The core properties and operation are controlled through a set of signals. They set the link speed during initialization and run-state, link interface FSM timeouts and control operations such as starting and disabling the link.

Compared to the GRSPW/GRSPW2 the core is useful in applications where the AMBA bus is not present, the source of data does not have an AMBA interface, low area is needed or when very detailed control of character transfer order and timing is needed.

Area and timing

The GRSPW_CODEC has been designed for high frequency operation even on slow technologies. The table below shows the approximate Cell/LUT count and frequency for three different GRSPW_CODEC configurations on Actel RTAX, RTProASIC3, Xilinx Virtex5 and ASIC technologies.

(Cells / RAM blocks / AHB MHz / SPW Rx Mbps)

Core configuration RTAX RTProASIC3L Virtex5  ASIC
GRSPW_CODEC 1,800 / 2 / 40 / 295 2,400 / 2 / 45 / 206 700 / 2 / 100 / 400  6,000 gates
GRSPW_CODEC+2P(1) 2,000 / 2 / 40 / 295 2,800 / 2 / 45 / 206 760 / 2 / 100 / 400 7,000 gates 
GRSPW_CODEC + 2P+FT(2) 2,100 / 2 / 40 / 295 2,900 / 2 / 45 / 206 800 / 2 / 100 / 400 7,400 gates   

  (1)Dual SpaceWire ports. One is available in the standard configuration,  (2) Fault tolerant version


  • Full implementation of SpacewWire standard (ECCS-E-ST-50-12C)
  • Simple 9-bit wide FIFO host interface
  • Redundant port
  • SEU protection fault-tolerance
  • Portable


  • Tested and verified against several other SpaceWire cores
  • High frequency
  • Easily portable between FPGA and ASIC
  • Low-cost project license
  • SEU protection of all RAM blocks


  • FPGA/ASIC netlist
  • Stand-alone testbench
  • User's manual