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SPI Controller
Status:
Available
The SPICTRL provides a link between the AMBA APB bus and the Serial Peripheral Interface (SPI) bus. Through registers mapped into APB address space the core can be configured to work either as a master or a slave.
Overview
The core provides a link between the AMBA APB bus and the Serial Peripheral Interface (SPI) bus. Through registers mapped into APB address space the core can be configured to work either as a master or a slave.
Architecture
Key Tech Spec
Target technology support
Evaluation boards
Ordering information
Development Kit
Licensing
Software
Tools
Block diagram
Supported Hardware
Configuration
Reference Design
Other resources
Detailed features
- AMBA APB interface
- Both master and slave operation
- Software programmable clock frequency
- Configurable FIFO depth
- Supports all SPI modes
- Configurable word length (4 - 32 bits, but the core supports back-to-back transactions and thereby allows longer words)
- Configurable bit ordering
- Clock gap insertion
Downloads
File
Category
Revision
Date
Access
Excel sheet for SoC area estimation
Data sheet and user's manual
2024.4
2024-12-23
Free download
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Frequently asked questions
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