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NOEL RISC-V Processors

NOEL3 examples

Status:

Available

Prebuilt NOEL3 processor bitstreams for several FPGA development boards. These bitstreams are intended for evaluation of software running on a NOEL3 RISC-V processor.

Overview

We provide example bitfiles for evaluate the NOEL3 RISC-V processor in the following FPGA development boards:

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To evaluate the example bitfiles the following items are required:

One of the evaluation boards above
Workstation with GNU/Linux or Microsoft Windows
Software to program the FPGA
Bitstream, available in the zip file further down on this page
GRMON evaluation version

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Architecture

Fault tolerance

Key Tech Spec

Target technology support

Evaluation boards

Development Kit

Licensing

Software

Tools

Block diagram

Related project

Supported Hardware

Configuration

Reference Design

Other resources

Detailed features

NOEL3 RISC-V processor:
- RV32I, M, A, F, B, Zicond, Zimop, Zifencei, Zicsr, Zicntr
- Barrel architecture with 3 hardware threads
- ITCM - Instruction Tightly Coupled Memory (size depends on the implementation)
- DTCM - Data Tightly Coupled Memory (size depends on the implementation)
UART
GPIO
Timer

Downloads

File

Category

Revision

Date

Access

NOEL3 & Example Bitfiles User's Manual

Data sheet and user's manual

1.0

2025-12-19

Free download

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NOEL3 Example Bitfiles

Example bitstream

1.0