Status:
Available
The DDR2SPA can interface two 16,32 or 64-bit wide DDR2 banks. Both memory and configuration register accesses are performed through an AHB slave interface.
DDR2SPA is a DDR2 SDRAM controller with AMBA AHB back-end. The controller can interface 16-, 32- or 64-bit wide DDR2 memory with one or two chip selects. The controller acts as a slave on the AHB bus where it occupies a configurable amount of address space for DDR2 SDRAM access. The DDR2 controller is programmed by writing to configuration registers mapped in the AHB I/O address space. Internally, DDR2SPA consists of an AHB/DDR2 controller and a technology-specific DDR2 PHY.
File
Category
Revision
Date
Access
Data sheet and user's manual
2025.1
2025-04-25
Free download
Password/
Contact us
Full ecosystem for mission critical System-on-a-Chip solutions
