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The DDRSPA can interface two 16,32 or 64-bit wide DDR266 banks. Both memory and configuration register accesses are performed through an AHB slave interface. The core also supports mobile DDR (LPDDR).
DDRSPA is a DDR266 SDRAM controller with AMBA AHB back-end. The controller can interface two 16-, 32-, or 64-bit DDR266 memory banks to a 32-bit AHB bus. The controller acts as a slave on the AHB bus where it occupies a configurable amount of address space for DDR SDRAM access. The DDR controller is programmed by writing to a configuration register mapped in the AHB I/O address space. Internally, DDRSPA consists of an AHB/DDR controller and a technology-specific DDR PHY.
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Data sheet and user's manual
2025.1
2025-04-25
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