Section Processors - Category LEON CPU Family

LEON3FT Fault-tolerant processor

Introduction

The LEON3FT is a fault-tolerant version of the standard LEON3 SPARC V8 Processor. It has been designed for operation in the harsh space environment, and includes functionality to detect and correct (SEU) errors in all on-chip RAM memories. The LEON3FT processor support most of the functionality in the standard LEON3 processor, and adds the following features:

  • Register file SEU error-correction of up to 4 errors per 32-bit word
  • Cache memory error-correction of up to 4 errors per tag or 32-bit word
  • Autonomous and software transparent error handling
  • No timing or performance impact due to error detection and correction

The following features of the standard LEON3 processor are NOT supported by LEON3FT

  • Local scratch pad RAM (I and D)
  • Cache locking
  • LRR cache replacement algorithm

Fault-tolerance scheme

The fault-tolerance in LEON3FT is implemented using ECC coding of all on-chip RAM blocks. The ECC codes are adapted to the type of RAM blocks that are available for a given target technology, and to the type of data that is stored in the RAM blocks. The general scheme is to be able to detect and correct up to four errors per 32-bit RAM word. In RAM blocks where the data is mirrored in a secondary memory area (e.g. cache memories), the ECC codes are tuned for error-detection only. A correction cycle consists then of reloading the faulty data from the mirror location. In the cache memories, this equals to an invalidation of the faulty cache line and a cache line reload from main memory.

In RAM blocks where no secondary copy of the data is available (e.g. register file), the ECC codes are tuned for both error-detection and correction. The focus is placed on fast encoding/decoding times rather than minimizing the number of ECC bits. This approach ensures that the FT logic does not affect the timing and performance of the processor, and that LEON3FT can reach the same maximum frequency as the standard non-FT LEON3. The ECC encoding/decoding is done in the LEON3FT pipeline in parallel with normal operation, and a correction cycle is fully transparent to the software without affecting the instruction timing.

The ECC protection of RAM blocks is not limited to the LEON3FT processor. In a SOC design based on LEON3FT, any IP core using block RAM will have the RAM protected in a similar manner. This includes for instance the FIFOs in the SpaceWire IP core (GRSWP) and the buffer RAM in the CAN-2.0 IP core (CAN_OC).

Simulation and synthesis

The LEON3FT is simulated and synthesized in the same manner as the standard LEON3 processor. The area overhead for the FT logic is less than 15% on both ASIC and FPGA implementations. The table below shows some typical area figures for ASIC and RTAX technologies:

 Core RTAX cells
RTAX RAM blocks
ASIC gates
 LEON3 8 + 8 Kbyte cache 6,500 40 20,000
 LEON3FT 8 + 8 Kbyte cache 7,500 40 22,000
 LEON3FT 8 + 4 Kbyte cache 7,500 31 22,000

Distribution

The LEON3FT core is distributed together with a special FT version of the GRLIP IP library, distributed as encrypted RTL.

Software development

Software development for LEON3FT is identical to the standard LEON3. The fault-tolerance implementation is fully software transparent, and no software drivers are necessary for its operation. See the LEON3 software page for more details. The LEON3 simulators (TSIM and GRSIM) as well as the GRMON debug monitor are fully compatible with LEON3FT.

Radiation-hardened devices based on LEON3FT

 Device  Manufacturer
 Frequency  MIPS
 GR712RC Dual-Core SOC  Aeroflex Gaisler  100 MHz  200 DMIPS
 UT699 Single-Core SOC  Aeroflex Colorado Springs   66 MHz   75 DMIPS
 LEON3FT-RTAX  Aeroflex Gaisler / Actel   25 MHz   20 DMIPS

LEON3FT implemented in RTAX2000S radiation-tolerant FPGA

The LEON3FT-RTAX processor is a SOC design based on LEON3FT, implemented in the RTAX2000S radiation-tolerant FPGA. In addition to the LEON3FT core, the LEON3FT-RTAX includes a number of application-specific IP cores. Four pre-defined configurations are available to address different application requirements. The LEON3FT-RTAX devices are shipped as pre-programmed and tested parts in all quality levels supported by Actel. Available packages are CQFP352 and CCGA624. More details on LEON3FT-RTAX is available on a dedicated page

LEON3 Processor

Introduction

The LEON3 is a synthesisable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture. The model is highly configurable, and particularly suitable for system-on-a-chip (SOC) designs. The full source code is available under the GNU GPL license, allowing free and unlimited use for research and education. LEON3 is also available under a low-cost commercial license, allowing it to be used in any commercial application to a fraction of the cost of comparable IP cores. The LEON3 processor has the following features:

  • SPARC V8 instruction set with V8e extensions
  • Advanced 7-stage pipeline
  • Hardware multiply, divide and MAC units
  • High-performance, fully pipelined IEEE-754 FPU
  • Separate instruction and data cache (Harvard architecture) with snooping
  • Configurable caches: 1 - 4 ways, 1 - 256 kbytes/way. Random, LRR or LRU replacement
  • Local instruction and data scratch pad RAM, 1 - 512 Kbytes
  • SPARC Reference MMU (SRMMU) with configurable TLB
  • AMBA-2.0 AHB bus interface
  • Advanced on-chip debug support with instruction and data trace buffer
  • Symmetric Multi-processor support (SMP)
  • Power-down mode and clock gating
  • Robust and fully synchronous single-edge clock design
  • Up to 125 MHz in FPGA and 400 MHz on 0.13 um ASIC technologies
  • Fault-tolerant and SEU-proof version available for space applications
  • Extensively configurable
  • Large range of software tools: compilers, kernels, simulators and debug monitors
  • High Performance: 1.4 DMIPS/MHz, 1.8 CoreMark/MHz (gcc -4.1.2)


The LEON3 processor is distributed as part of the GRLIB IP library, allowing simple integration into complex SOC designs. GRLIB also includes configurable LEON3 multi-processor designs and several on-chip peripheral blocks.

Configuration

The LEON3 processor is fully prametrizable through the use of VHDL generics, and does not rely on any global configuration package. It is thus possible to instantiate several processor cores in the same design with different configurations. The LEON3 template designs can be configured using a graphical tool built. This allows new users to quickly define a suitable custom configuration. The configuration tool not only configures the processor, but also other on-chip peripherals such as memory controllers and network interfaces.

tkconfig

Synthesis

The LEON3 processor can be synthesised with common synthesis tools from vendors such as Synopsys, Mentor, Xilinx and Altera.

Probabilistic platform

The LEON3 processor was extended within the PROXIMA project to build a platform with hardware support that enables probabilistic timing analysis. These extensions, including extensions for GRLIB's Level-2 cache, can also be obtained from Cobham Gaisler.

Distribution

LEON3 is distributed as part of the GRLIB IP library, and the library contains LEON3 templates designs for several popular FPGA prototyping boards. Pre-synthesized FPGA programming files are also provided.

SPARC Conformance

LEON3 has been certified by SPARC International as being SPARC V8 conformant. The certification was completed on May 1, 2005.

sparc-cert

Software development

Being SPARC V8 conformant, compilers and kernels for SPARC V8 can be used with LEON3 (kernels will need a LEON bsp). To simplify software development, Cobham Gaisler provides several toolchains and operating systems.

Debugging is generally done using the gdb debugger, and a graphical front-end such as DDD or Eclipse. It is possible to perform source-level symbolic debugging, either on a simulator or using real target hardware. Cobham Gaisler provides TSIM, a high-performance LEON3 simulator which seamlessly can be attached to gdb and emulate a LEON3 system. The GRMON monitor interfaces to the LEON3 on-chip debug support unit (DSU), implementing a large range of debug functions as well as a GDB gateway. For multi-processor and/or advanced SOC designs, the GRSIM multi-core simulator is available for early software development.

Community

Cobham Gaisler AB maintains a Discourse forum for those interested in the open source company's processor products.

LEON4 Processor

Introduction

The LEON4 is a synthesizable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture. The model is highly configurable, and particularly suitable for system-on-chip (SOC) designs. LEON4 is also available under a low-cost commercial license, allowing it to be used in any commercial application to a fraction of the cost of comparable IP cores.

The LEON4 is interfaced using the AMBA 2.0 AHB bus and supports the IP core plug&play method provided in the Cobham Gaisler IP library (GRLIB). The processor can be efficiently implemented on FPGA and ASIC technologies and uses standard synchronous memory cells for caches and register file. The processor supports the MUL, MAC and DIV instructions and an optional IEEE-754 floating-point unit (FPU) and Memory Management Unit (MMU).

The LEON4 cache system consists of separate I/D multi-set Level-1 (L1) caches with up to 4 ways per cache, and an optional Level-2 (L2) cache for increased performance in data intensive applications.

The LEON4 pipeline uses 64-bit internal load/store data paths, with an AMBA AHB interface of either 64- or 128-bit. Branch prediction, 1-cycle load latency and a 32x32 multiplier results in a performance of 1.7 DMIPS/MHz, or 2.1 CoreMark/MHz.

The LEON4 processor has the following features:

  • SPARC V8 instruction set with V8e extensions
  • Advanced 7-stage pipeline, with branch prediction
  • 64-bit single-clock load/store operation
  • 64-bit 4-port register file
  • Hardware multiply, divide and MAC units
  • High-performance, fully pipelined IEEE-754 FPU
  • Separate instruction and data L1 cache (Harvard architecture) with snooping
    • Configurable caches L1: 1 - 4 ways, 1 - 256 kbytes/way. Random, LRR or LRU replacement
  • Configurable L2 cache: 256-bit internal, 1-4 ways, 16 Kbyte - 8 Mbyte
  • SPARC Reference MMU (SRMMU) with configurable TLB
  • AMBA-2.0 AHB bus interface, 64- or 128-bit wide
  • Advanced on-chip debug support with instruction and data trace buffer, and performance counter
  • Symmetric Multi-processor support (SMP)
  • Power-down mode and clock gating
  • Robust and fully synchronous single-edge clock design
  • Up to 150 MHz in FPGA and 1500 MHz on 32 nm ASIC technologies
  • Extensively configurable
  • Large range of software tools: compilers, kernels, simulators and debug monitors
  • High performance: 1.7 DMIPS/MHz, 2.1 CoreMark/MHz, 0.35 (estimated) SPECint2000/MHz

Configuration

The LEON4 processor is fully parameterizable through the use of VHDL generics, and does not rely on any global configuration package. It is thus possible to instantiate several processor cores in the same design with different configurations.

Synthesis

The LEON4 processor can be synthesized with common synthesis tools such as Synplify, Synopsys DC and Cadence RC. The core area (pipeline, cache controllers and mul/div units) requires only 30 kgates or 4000 LUT, depending on the configuration. The LEON4 processor can also be synthesized with Mentor Precision, Xilinx XST and Altera Quartus, either through scripts or by using the graphical interfaces of the tools.

Software development

Being SPARC V8 conformant, compilers and kernels for SPARC V8 can be used with LEON4 (kernels will need a LEON BSP). To simplify software development, Cobham Gaisler provides several toolchains and operating systems.

Debugging is generally done using the gdb debugger, and a graphical front-end such as DDD or Eclipse. It is possible to perform source-level symbolic debugging, either on a simulator or using real target hardware. Cobham Gaisler provides TSIM, a high-performance LEON4 simulator which seamlessly can be attached to gdb and emulate a LEON4 system at more than 30 MIPS. The GRMON monitor interfaces to the LEON4 on-chip debug support unit (DSU), implementing a large range of debug functions as well as a GDB gateway. For multi-processor and/or advanced SOC designs, the GRSIM multi-core simulator is available for early software development.