Gaisler Releases RISC-V Processor IP Core

We have has announced at the RISC-V Summit in San Jose, California, that we will release a new line of processor Intellectual Property (IP) cores that implements the RISC-V instruction set architecture (ISA). The NOEL-V processor IP core, the first product in the family, will be made available on 25 December for download into Xilinx’ Kintex UltraSCALE FPGAs.

Read the press release