Cobham Gaisler AB provides IP cores and supporting development tools for embedded processors based on the SPARC architecture. We specialize in digital hardware design for both commercial and aerospace applications

Synplicity's ReadyIP Program

Synplicity's ReadyIP program delivers the industry's first and complete universal, encrypted design methodology for FPGA implementation, allowing users to incorporate and easily integrate IP from several third-party vendors within their designs using the Synplify Pro® and/or Synplify® Premier solutions, Synplicity's industry-standard synthesis environments.

Amongst others, the ReadyIP program provides "push-button" Internet access to third-party IP directly from within Synplicity's FPGA design environment. Cobham Gaisler make available three sets of IP cores in source code through the ReadyIP program, as listed hereafter.  The IP cores can be accessed via the Synplify Pro® and/or Synplify® Premier tools.


  • Cobham Gaisler LEON3 and GRLIB IP core library (production version)

SPARC V8 compliant 32-bit processor core and AMBA based IP core library

  • The download includes the following source code:

LEON3 - SPARC V8 32-bit processor

DSU3 - Multi-processor Debug support unit

IRQMP - Multi-processor Interrupt controller

AHBCTRL - AMBA AHB bus controller with plug&play

APBCTRL - AMBA APB Bridge with plug&play

AHBJTAG - JTAG/AHB debug interface

AHBUART - Serial/AHB debug interface

AHBRAM - Single-port RAM with AHB interface

AHBROM - ROM generator with AHB interface

AHBSTAT - AHB failing address register

AHBTRACE - AMBA AHB Trace buffer

APBPS2 - PS2 Keyboard interface with APB interface

APBUART - Programmable UART with APB interface

DDRCTRL - 8/16/32/64-bit DDR controller with two AHB ports

DDRSPA - Single-port 16/32/64 bit DDR266 controller

SDCTRL - PC133 SDRAM controller

SRCTRL - 8/32-bit PROM/SRAM controller

GRETH - 10/100 Mbit Ethernet MAC with AHB I/F

I2CMST - I2C Master with APB interface

PCIDMA - DMA controller for PCIMTF

PCIMTF/GRPCI - 32-bit PCI master/target interface with FIFO

PCITARGET - 32-bit target-only PCI interface

PCITRACE - 32-bit PCI trace buffer

SPICTRL - SPI Controller with APB interface

REGFILE_3P - Parametrizable 3-port register file

SYNCRAM - Parametrizable 1-port RAM

SYNCRAM_2P - Parametrizable 2-port RAM

SYNCRAM_DP - Parametrizable dual-port RAM

AHBMSTEM - AHB master simulation model with scripting

AHBSLVEM - AHB slave simulation model with scripting

SRAM - SRAM simulation model with srecord pre-load

GRFPU - High-performance IEEE-754 Floating-Point Unit (netlists for Xilinx, Altera) (license)

GRLIB User's Manual

GRLIB IP Cores Manual


  • IP cores for Synplicity's High-performance ASIC Prototyping System (HAPS)  (production version)

IP cores for the HAPS-31, HAPS-51, HAPS-52 and HAPS-54 motherboards and several daughter boards

  • The download includes the following source code:

HAPSTRAK - HapsTrak controller for HAPS boards

BIO1 - Controller for HAPS I/O board BIO1

GEPHY_1X1 - Ethernet Controller for HAPS GEPHY_1x1

DDR_1X1 - 64-bit DDR266 Controller for HAPS DDR_1x1

FLASH_1X1 - 32/16-bit PROM Controller for HAPS FLASH_1x1

SDRAM_1X1 - 32-bit SDRAM Controller for HAPS SDRAM_1x1

SRAM_1X1 - 32-bit SSRAM / PROM Controller for HAPS SRAM_1x1

TEST_1X2 - Controller for HAPS test daughter board TEST_1x2 

Synplicity HAPS IP Cores Manual


  • IP cores for spacecraft Telemetry and Telecommand (production version)

IP cores for CCSDS/ECSS telemetry and telecommand functions

  • The download includes the following source code:

GRTC - CCSDS Telecommand decoder

GRCTM - CCSDS Time manager

GRPW - PacketWire receiver with AHB interface

APB2PW - PacketWire Transmitter Interface

PW2APB - PacketWire Receiver Interface

Spacecraft TM/TC IP Cores Manual