"The complexity of the designs that are made in FPGAs has increased at the same rate as for ASICs. In essence, the FPGA design task has become much more complex. It has never before been so easy to make so many mistakes so fast as now."
Starting from a summary of things which went wrong in real life ("lessons learned"), this document is an extension to the two previous documents, suggesting a development/design methodology for FPGA and valuable recipees for single event mitigation in FPGA designs. Author: Sandi Habinc.