Cobham Gaisler AB provides IP cores and supporting development tools for embedded processors based on the SPARC architecture. We specialize in digital hardware design for both commercial and aerospace applications

Low power error resilient encoding for on-chip data buses

[Download] (DATE2002)
Bertozzi, D.; Benini, L.; De Micheli, G.

As technology scales toward deep submicron, on-chip interconnectsare becoming more and more sensitive to noisesources such as power supply noise, crosstalk, radiationinduced effects, etc. Transient delay and logic faults arelikely to reduce the reliability of data transfers across data-pathbus lines. This paper investigates how to deal withthese errors in an energy efficient way. We could opt forerror correction, which exhibits larger decoding overhead,or for the retransmission of the incorrectly received dataword. Provided the timing penalty associated with this lattertechnique can be tolerated, we show that retransmissionstrategies are more effective than correction ones from anenergy viewpoint, both for the larger detection capabilityand for the minor decoding complexity. The analysis was performed by implementing several variants of a Hammingcode in the VHDL model of a processor based on the SparcV8 architecture (LEON2), and exploiting the characteristics of AMBA bus slave response cycles to carry out retransmissions in away fully compliant with this standard on-chip bus specification.