eFPGA
The GR765 includes a radiation-hardened embedded FPGA (eFPGA) with 32k LUTs . Directly interfacing with SpaceFibre and WizardLink communication interfaces, the eFPGA can optimize data decimation tasks and offer efficient in-hardware processing. The eFPGA is also well-suited for implementing glue logic to connect with custom external interfaces. Being radiation-hardened there is no need to apply Triple Modular Redundancy (TMR) or scrubbing to the eFPGA designs. The GRLIB IP Library includes a collection of VHDL IP cores optimized for the eFPGA.
Security
The GR765 includes an isolated SoC that can be used for system control and security functions acting as a Hardware Security Module (HSM), operating independently from the main system.
Capabilities:
- Authenticated boot for OS and software assets
- Unique device identification
- Hardware-based root of trust
- Secure message signing, verification and encryption
- Key management and cryptographic operations
- Integrated crypto accelerators for performance optimization
- Support for Post-Quantum Cryptography (PQC) algorithms
Firmware:
- Managed by firmware under the system integrator’s control
- Example firmware provided with GR765
- Firmware can be customized or replaced with third-party certified solutions
Furthermore, the GR765 features logic for quantum- secure authenticated boot, implemented without any software components. The core combines
ECDSA and ML-DSA signature schemes to verify the authenticity and integrity of binary images loaded into the system during the boot sequence.
The architecture includes additional security features such as functional and timing isolation through features in the on-chip interconnect, processor memory management units, and an IO bridge with an IO Memory Management Unit and IO Physical Memory Protection functionality.
In NOEL-V RISC-V mode, the architecture also has support for the RISC-V Control Flow Integrity extensions.
On-chip high-speed memory interconnect
The on-chip striped interconnect between the processor cores and the L2 cache and between the L2 cache and the DDR memory controller allow concurrent accesses to different L2 cache memory banks and DDR memory. This feature increases the bandwidth and minimizes interference between cores. The system can be configured in an isolated mode that makes useof the dedicated communication channels to remove inter-core interference for memory accesses and simplifies worst-case execution time (WCET) analysis.
SpaceFibre and SpaceWire
The SpaceWire router is also integrated with the SpaceFibre controller. SpaceWire data from/to multiple payloads can be aggregated in a single SpaceFibre High Speed Serial Link without software intervention.
