The GRSPWROUTER IP core is a VHDL model of a SpaceWire routing switch as defined in the ECSS-E-ST-50-12C standard. The core is highly configurable, flexible and portable to a wide variety of FPGA and ASIC technologies. The core supports all mandatory and optional features in the ECSS-E-ST-50-12C standard and can be configured from the minimum number of ports 2 to the maximum 31. In addition to this there is the mandatory configuration port. The configuration port provides access to configuration and status registers and the routing table using the Remote Memory Access Protocol (RMAP) defined in ECSS-E-ST-50-52C. The SpaceWire Plug-and-Play (PnP) protocol can optionally be supported on the configuration port.
The different port types along with the high degree of configurability and technology support makes the core very suitable in a wide range of different systems and makes it possible for designers to optimize area and performance. It can be made as a standalone router ASIC, FPGA or as part of an AMBA bus based processor system. In each case the router core and configuration space will be the same making it easy to migrate to new systems. The core provides numerous interfacing possibilities.
A wide range of configuration registers and signals are provided, allowing the user to have full control of the router, for example to disable configuration accesses from certain ports or to filter time-code propagation.
Area and timing
The table below shows the approximate gate count and frequency for different GRSPWROUTER configurations on Actel RT ProASIC3, Actel RTAX, and Xilinx Virtex 4 technologies.
|Core configuration||Actel RT ProASIC3
||Actel RTAX||Xilinx Virtex 4
|Area||40700 VersaTiles/50 RAM512x18||21500 C/10200 R/26 RAM64K36||78000 LUT/75 RAM|
|Core clock||30 MHz||25 MHz||50 MHz|
|Link rate||180 Mbit/s||200 Mbit/s||200 Mbit/s|