Cobham Gaisler AB provides IP cores and supporting development tools for embedded processors based on the SPARC architecture. We specialize in digital hardware design for both commercial and aerospace applications


I2C2AHB block diagram The I²C slave to AHB bridge core is a I²C slave that provides a link between the I²C bus and AMBA AHB. The core is compatible with the Philips I²C standard.

On the I²C bus the slave acts as an I²C memory device where accesses to the slave are translated to AMBA accesses. The core can translate I²C accesses to AMBA byte, halfword or word accesses. The core makes use of I²C clock stretching but can also be configured to use a special mode with clock stretching in order to support systems where limitations of the master or physical layer prevent stretching of the I²C clock period.


  • AMBA AHB interface
  • Optional APB interface for software configuration
  • Optional programmable I²C addresses - The initial addresses are configurable via VHDL generics. The designer can choose to leave the core's address programmable via an APB mapped register.
  • Can map the full 4 GiB AMBA address space or an address range specified by the designer at implementation, or by software via the optional APB interface.
  • Optional clock stretching

For more information, please see the GRLIB IP Core User's Manual


  • The core is available under a commercial license and also under the GPL.