Cobham Gaisler AB provides IP cores and supporting development tools for embedded processors based on the SPARC architecture. We specialize in digital hardware design for both commercial and aerospace applications


Quad-Core LEON4  Evaluation Board

Note: The GR-CPCI-LEON4-N2X board is out of stock and no further production is planned. Please see the GR-CPCI-GR740 development board instead.

The GR-CPCI-LEON4-N2X evaluation board has been designed for evaluation of the Cobham Gaisler LEON4 Next Generation Microprocessor (NGMP) functional prototype device. The prototype is a system-on-chip with four 32-bit LEON4 SPARC V8 processor cores connected to a shared 256 KiB Level-2 cache and several high-speed interfaces, including an 8-port SpaceWire router and dual gigabit Ethernet interfaces. The architecture provides improved support for debugging and software partitioning together with extended support for both symmetric and asymmetric multiprocessing. The space-grade successor for this NGMP functional prototype is the Rad-Hard GR740 device. There are several differences between the GR740 device and the LEON4-N2X functional prototype and users who intend to target GR740 are recommended to use the GR-CPCI-GR740 development board.

The board is a custom designed PCB in a 6U Compact PCI (CPCI) format, making the board suitable for stand-alone bench top development, or if required, to be mounted in a 6U CPCI Rack. The principle interfaces and functions are accessible on the front and back edges of the board, and secondary interfaces via headers on the board.



  • Quad-Core 32-bit LEON4 SPARC V8 processor
  • 6U Compact PCI format
  • On board memory

- DDR2 SDRAM SODIMM sockets, providing 96-bit wide interface with up to 2 GiB of data memory
- PC100 SDRAM, 96-bit wide interface providing 128 MiB of data memory
- NOR Flash PROM, 8 MiB, both 8- and 16-bit wide operation

  • Debug communication links: SpaceWire, USB 2.0, Ethernet, JTAG
  • Interfaces at front edge of board:

- Dual 10/100/1000 Mbit Ethernet interface
- Dual-redundant MIL-STD-1553B interface
- 8-port SpaceWire interface
- SpaceWire Debug Communication Link interface
- 16 bit General Purpose I/O (ribbon cable style connector)
- USB-to-Serial interface providing access to UARTs and JTAG debug interface

  • Interfaces at back edge of board:

- Compact PCI interface (32 bit, 33/66MHz), configurable for Host or Peripheral slot
- Input power connectors for stand-alone use

  • Interfaces on board:

- DIP switches for GPIO and bootstrap signal configuration
- LED indicators
- SPI interface
- Two Serial UART interface (RS232)
- JTAG debug interface

GR-CPCI-LEON4-N2X diagram


  • Cobham Gaisler LEON4-N2X (NGMP functional prototype) in FC896 package
  • Processor core frequency: 150 MHz
  • Compact PCI 6U form factor (233.5mm x 160mm) 
  • Memory

- DDR2-600 SDRAM, 1 bank 96 bits wide, DDR2-SODIMM sockets
- PC100 SDRAM, 1 bank 96 bits wide, 6x256 Mbit, discrete chips
- Parallel Boot Flash (64 Mbit, both 8- and 16-bit wide operation)

  • Dual RJ45 10/100/1000 Mbit GMII/MII Ethernet interface (KSZ9021GN with RJ45 jack)
  • 8 SpaceWire interfaces (MDM9S)
  • SpaceWire Debug Communication Link (MDM9S)
  • USB 2.0 Debug Communication Link (ISP1504A with USB Mini-AB) interface
  • 16 bit General Purpose I/O (34 pin 0.1” ribbon cable style connector)
  • Dual-redundant MIL-STD-1553B Interface (DE9)
  • FTDI Serial to USB interface (FT2232H with USB Mini-AB)
  • DIP switches for GPIO signal configuration
  • DIP switch for Memory interface configuration
  • SPI interface user connections on 0.1” header
  • SPI Temperature Sensor
  • Two Serial UART interface (RS232) with DE9 female connectors
  • JTAG Debug Communication Link
  • Test connector for boundary scan
  • 4-pin Molex style and 2.1 mm jack power connectors
  • Push buttons for RESET and BREAK
  • LED indicators for POWER, ERRORN, DSU active and GPIO
  • Assorted jumpers and test points for configuration and test of the board
  • Power, reset, clock and auxiliary circuits
  • MMCX connectors for external clock sources
  • AMP connector for memory mapped I/O


There are differences in between the GR740 device and the NGMP functional prototype and these are described in the GR740 Comparison document available on the GR740 product page.

Document File
GR-CPCI-LEON4-N2X Quick Start Guide GR-CPCI-LEON4-N2X-QSG.pdf (updated 2013-July)
GR-CPCI-LEON4-N2X Board Package (updated 2013-July)
GR-CPCI-LEON4-N2X Board User Manual GR-CPCI-LEON4-N2X_UM.pdf (updated 2018-March)
LEON4-N2X Data Sheet and User's Manual LEON4-N2X-DS.pdf (updated 2015-April)
Technical Note on LEON SRMMU Behaviour GRLIB-TN-0002.pdf
Handling denormalized numbers with the GRFPU GRLIB-AN-0007.pdf