GR-RASTA is a development/evaluation platform for LEON2, LEON3 and LEON4 based spacecraft avionics. Processing is provided by the LEON3 processor pre-programmed into either an Actel Axcelerator or a Xilinx Virtex4 FPGA. Interfaces such as SpaceWire, MIL-STD-1553B, CAN 2.0B and CCSDS TM/TC are provided on separate FPGA I/O boards. Communication between the boards is done via the Compact PCI (cPCI) bus. The system is shipped ready to use in a cPCI crate together with cabling, documentation and demonstration software.
The are three available options for the cPCI host system.
Different I/O boards are available, as listed hereafter.
This configuration can optionally be fitted with a LEON3 or LEON2 and run standalone without the need for a cPCI host CPU.
Note that for the Axcelerator board all interfaces do not fit into the FPGA at once but all possible options are listed.
This board is connected with a ribbon cable to a main I/O board and provides
This board is connected with a ribbon cable to a main I/O board.
Interface specifications and connectors
GR-RASTA standard configurations
Note: For the GR-RASTA-105 configuration, it is possible to include GRLIB CCSDS/ECSS TM encoder and TC decoder inside the FPGA on the GR-CPCI-XC4V board, adding a GR-TMTC-ADAPTER accessory board with RS422 drivers for transponder communication. Please contact us for details.