GR-RASTA - LEON2/3/4 spacecraft avionics development platform


GR-RASTA is a development/evaluation platform for LEON2, LEON3 and LEON4 based spacecraft avionics. Processing is provided by the LEON3 processor pre-programmed into either an Actel Axcelerator or a Xilinx Virtex4 FPGA. Interfaces such as SpaceWire, MIL-STD-1553B, CAN 2.0B and CCSDS TM/TC are provided on separate FPGA I/O boards. Communication between the boards is done via the Compact PCI (cPCI) bus. The system is shipped ready to use in a cPCI crate together with cabling, documentation and demonstration software.

cPCI host controller boards

The are three available options for the cPCI host system.

  • LEON3 processor pre-programmed into Xilinx Virtex4 FPGA (GR-CPCI-XC4V)
  • LEON3 processor pre-programmed into Actel Axcelerator FPGA (GR-CPCI-AX2000)

cPCI I/O boards

Different I/O boards are available, as listed hereafter.

Interface specifications and connectors

  • SpaceWire: up to 200 Mbps, LVDS, MDM9-S connectors
  • MIL-STD-1553B: A/B buses with Twinax BJ75 connectors
  • CAN 2.0B: ISO11898, 2 buses with 9-pin D-Sub (male) connectors
  • CCSDS Telemetry and Telecommand: RS422, HD26 connectors
  • PacketWire: RS422, HD15 connectors
  • UART: RS232, 9-pin D-sub (female) connector
  • Ethernet: 10/100 Mbps, RJ45 connector
  • PCI: 33 MHz, 32-bit, 3.3 V cPCI connector

GR-RASTA standard configurations

RASTA configurations

Note: For the GR-RASTA-105 configuration, it is possible to include GRLIB CCSDS/ECSS TM encoder and TC decoder inside the FPGA on the GR-CPCI-XC4V board, adding a GR-TMTC-ADAPTER accessory board with RS422 drivers for transponder communication. Please contact us for details.