LEON3 Processor
Introduction
The LEON3 is a synthesisable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture. The model is highly configurable, and particularly suitable for system-on-a-chip (SOC) designs. The full source code is available under the GNU GPL license, allowing free and unlimited use for research and education. LEON3 is also available under a low-cost commercial license, allowing it to be used in any commercial application to a fraction of the cost of comparable IP cores. The LEON3 processor has the following features:
- SPARC V8 instruction set with V8e extensions
- Advanced 7-stage pipeline
- Hardware multiply, divide and MAC units
- High-performance, fully pipelined IEEE-754 FPU
- Separate instruction and data cache (Harvard architecture) with snooping
- Configurable caches: 1 - 4 ways, 1 - 256 kbytes/way. Random, LRR or LRU replacement
- Local instruction and data scratch pad RAM, 1 - 512 Kbytes
- SPARC Reference MMU (SRMMU) with configurable TLB
- AMBA-2.0 AHB bus interface
- Advanced on-chip debug support with instruction and data trace buffer
- Symmetric Multi-processor support (SMP)
- Power-down mode and clock gating
- Robust and fully synchronous single-edge clock design
- Up to 125 MHz in FPGA and 400 MHz on 0.13 um ASIC technologies
- Fault-tolerant and SEU-proof version available for space applications
- Extensively configurable
- Large range of software tools: compilers, kernels, simulators and debug monitors
- High Performance: 1.4 DMIPS/MHz, 1.8 CoreMark/MHz (gcc -4.1.2)
The LEON3 processor is distributed as part of the GRLIB IP library, allowing simple integration into complex SOC designs. GRLIB also includes configurable LEON3 multi-processor designs and several on-chip peripheral blocks.
Configuration
The LEON3 processor is fully prametrizable through the use of VHDL generics, and does not rely on any global configuration package. It is thus possible to instantiate several processor cores in the same design with different configurations. The LEON3 template designs can be configured using a graphical tool built. This allows new users to quickly define a suitable custom configuration. The configuration tool not only configures the processor, but also other on-chip peripherals such as memory controllers and network interfaces.
Synthesis
The LEON3 processor can be synthesised with common synthesis tools from vendors such as Synopsys, Mentor, Xilinx and Altera.
Probabilistic platform
The LEON3 processor was extended within the PROXIMA project to build a platform with hardware support that enables probabilistic timing analysis. These extensions, including extensions for GRLIB's Level-2 cache, can also be obtained from us.
Distribution
LEON3 is distributed as part of the GRLIB IP library, and the library contains LEON3 templates designs for several popular FPGA prototyping boards. Pre-synthesized FPGA programming files are also provided.
SPARC Conformance
LEON3 has been certified by SPARC International as being SPARC V8 conformant. The certification was completed on May 1, 2005.
Software development
Being SPARC V8 conformant, compilers and kernels for SPARC V8 can be used with LEON3 (kernels will need a LEON bsp). To simplify software development, we provide several toolchains and operating systems.
Debugging is generally done using the gdb debugger, and a graphical front-end such as DDD or Eclipse. It is possible to perform source-level symbolic debugging, either on a simulator or using real target hardware. We provide TSIM, a high-performance LEON3 simulator which seamlessly can be attached to gdb and emulate a LEON3 system. The GRMON monitor interfaces to the LEON3 on-chip debug support unit (DSU), implementing a large range of debug functions as well as a GDB gateway. For multi-processor and/or advanced SOC designs, the GRSIM multi-core simulator is available for early software development.
Community
We maintain a Discourse forum for those interested in the open source company's processor products.