Cobham Gaisler AB provides IP cores and supporting development tools for embedded processors based on the SPARC architecture. We specialize in digital hardware design for both commercial and aerospace applications

Gaisler Research has increased its number of scientific FPGA designs in Earth orbit


Gaisler Research AB announced that it has designed several FPGAs for scientific experiments and instrument, all based on Actel RT54SX32 and RT54SX72S devices. The latest designs were launch on-board the Atlantis STS-122 shuttle mission and installed on the European Columbus laboratory that is part of the International Space Station (ISS).

Material Exposure and Degradation ExperimenT (MEDET) 

The latest contribution are the two FPGA designs that control the Material Exposure and Degradation ExperimenT (MEDET) which was launched on 7 February 2008 aboard the Atlantis STS-122 shuttle mission together with the European Columbus laboratory on its way to International Space Station (ISS). 

MEDET is part of the European Technology Exposure Facility (EuTEF) which is a technology and scientific mission initiative of the European Space Agency (ESA) to provide to the science community easy and low cost access to the external environment of ISS.  

MEDET will actively monitor material degradation dynamics in low Earth orbit and acquire information about the ISS environment in terms of contamination, atomic oxygen, ultraviolet and radiation, micrometeoroids and debris. 

Gaisler Research has designed the instrument controller, based on two Actel RT54SX72S FPGA devices, which manages the complete MEDET instrument. The instrument controller implements the communication protocol towards the Mil-Std-1553B bus interface circuit and the detailed control and management of the seven sub-experiments. 

- “The two MEDET FPGAs are good examples of complex designs that we have developed for the science community over the years. They basically implement all the control and management logic required by the MEDET instrument and its seven sub-experiments” stated Sandi Habinc, Senior Vice President of Engineering, Gaisler Research.  

Solar Electron Proton Telescope (SEPT)  

Gaisler Research has developed the instrument controller for the European Solar Electron Proton Telescope (SEPT) instrument. The SEPT instrument is part of the overall IMPACT (In-Situ Measurements of Particles and CME Transients) experiment package.  

Gaisler Research has designed the Actel RT54SX32S FPGA that controls the complete SEPT instrument, implementing the UART based communication protocol towards the IMPACT instrument control and the four Particle Detector Front-End (PDFE) ASICs that interface the silicon based telescope detectors. 

Four SEPT instruments are part of the IMPACT experiment package onboard the NASA Solar Terrestrial Relations Observatory (STEREO) mission that comprises two satellites orbiting the Sun. The two STEREO satellites were launched on 25 October 2006 aboard a Delta II rocket. Scientific results from the SEPT instruments have already been published and more are in progress. 

- “The SEPT instrument controller design is similar to that of MEDET since both control the complete instrument, including the experiment management and the communication with the experiment package. This experience from designing with space quality FPGAs has been useful in the development of our LEON3-FT offering for the Actel RTAX2000S FPGAs” stated Sandi Habinc.


MEDET picture on NASA web site: 

Columbus picture on ESA web site showing EuTEF/MEDET in lower left corner: 

MEDET and EuTEF on ESA web site:  

SEPT picture on Berkeley web site: 

SEPT on Berkeley web site: 

SEPT on ESA web site:

About Gaisler Research AB
Gaisler Research AB is a provider of SoC solutions for exceptionally competitive markets such as Aerospace, Military and demanding Commercial applications. The Gaisler Research's products consist of user-customizable 32-bit SPARC V8 processor cores, peripheral IP cores and associated software and development tools. Gaisler Research solutions help companies develop highly competitive customer and application-specific SoC designs.