|
Welcome
to the GRLIB IP Library
The GRLIB IP Library
is an integrated set of reusable IP cores, designed for system-on-chip
(SOC) development. The IP cores are centered around the common on-chip
bus, and use a coherent method for simulation and synthesis. The
library is vendor independent, with support for different CAD tools and
target technologies. A unique plug&play method is used to configure
and connect the IP cores without the need to modify any global
resources.
The
library includes cores for AMBA AHB/APB control, the LEON3 SPARC
processor, 32-bit PC133 SDRAM controller, 32-bit PCI bridge with DMA,
10/100/1000 Mbit ethernet MAC, ATA controller, 16/32/64-bits DDR controller, USB-2.0 Debug
link, TAP controller, CAN-2.0 core, 8/16/32-bit PROM and SRAM
controller, SVGA frame buffer, generic
UART, modular timer unit, interrupt controller, and a 32-bit GPIO port.
Memory and pad generators are available for Virage, Xilinx, UMC, Atmel,
Altera, Lattice, and Actel.
Documentation
DesignsGRLIB contains LEON3 template designs and bitfiles for the following FPGA boards
Xilinx
Actel
Altera
Lattice
The following template designs are also provided:
- PCI test bench with 5 PCI initiator/targets
- Netcard - Simple
example of a PCI-based network card (10/100 Mbit ethernet)
|