Standalone operation and remote connection to GNU debugger (gdb)
64-bit time for unlimited simulation periods
Loadable modules to include user-defined I/O device
Instruction trace buffer
Stack backtrace with symbolic information
Non-intrusive execution time profiling
Unlimited number of beakpoints and watchpoints
Check-pointing capability to save and restore complete simulator state
Code coverage monitoring
EDAC operation (TSIM2/ERC32)
NEW: MMU emulation (LEON2/LEON3)
NEW: Emulation of UT699, AT697 and AT7913E (Spw-RTC)
TSIM is available in three configurations: ERC32, LEON2 and LEON3 emulation.
Four host platforms are supported: linux, linux-x86-64, solaris and windows.
TSIM can be run in stand-alone mode, or connected through a network socket to the GNU gdb debugger. In stand-alone mode, a variety of debugging commands are available to allow manipulation of memory contents and registers, breakpoint/watchpoint insertion and performance measurement. Connected to gdb, TSIM acts as a remote target and supports all gdb debug requests. The communication between gdb and TSIM is performed using the gdb extended-remote protocol. Any third-party debugger supporting this protocol can be used.
The screen-shot shows TSIM connected to DDD/gdb (click on image for a larger view).
Timing
The simulator is cycle true, i.e a simulator time is maintained and incremented according the IU and FPU instruction timing. The parallel execution between the IU and FPU is modelled, as well as stalls due to operand dependencies. Instruction timing has carefully been modelled after the real devices and average timing accuracy of integer instructions is better than 0.5%. Floating-point instructions have a typical accuracy of 2% due to the somewhat unpredictable operand-dependent timing of the ERC32 and LEON MEIKO FPU. The simulator time is maintained using 64-bit values providing virtually unlimited simulation time.
ERC32 emulation
The ERC32 version of TSIM emulates both TSC691/2/3 chip-set and TSC695 from Atmel-Nantes (was TEMIC). The full behaviour of the devices is accurately emulated, including the memory EDAC functionality (TSIM2). The amount of simulated memory is can be configured at run-time. The memory size is limited by the ERC32 architecture: 256K - 32M ram, 128K - 4M rom. Access to unimplemented MEC registers or non-existing memory will correctly result in a memory exception trap. MEC register parity errors are also emulated when unused register bits are written.
LEON2/3 emulation
The full functionality of the LEON2 or LEON3 VHDL model is emulated, including cache memories, on-chip peripherals and memory controller. The amount of simulated main memory can be configured at run-time and is only limited by the resources of the host computer. The cache size and organisation can be configured between 1 - 64 kbyte/set, 1 - 4 sets, random/LRR/LRU replacement and 8 - 32 bytes/line. The multiplier latency can be programmed for 1 - 35 cycles.
I/O emulation
TSIM has a unique capability to simulate user-defined I/O devices. The user can provide a module emulating an I/O device, which is loaded by TSIM at run-time. The I/O module has access to the simulator event queue, interrupts and other internal data structures, allowing for accurate and timing true emulation. The I/O module is typically written in C, and can use any features of the host operating system. This provides high simulation performance and capability to communicate with simulator frameworks such as EUROSIM or SIMSAT. A report describing the emulation of an ERC32-specific ASIC can be found here. TSIM/LEON also has an optional AHB I/O module, allowing to add or replace peripheral devices connected to the on-chip AHB bus.
Device emulation
To simplify emulation of existing LEON2/3 devices, TSIM includes pre-compiled modules to emulate the following devices:
TSIM can also be provided as a static library (dll for windows), which can be linked into a larger user applications. The library provides access to all simulator internals and supports all TSIM commands and operations. An I/O interface is provided with the same structure as for the loadable modules.
Profiling
The TSIM profiling function calculates the amount of (target processor) execution time spent in each function of the emulated application. This is done in a non-intrusive manner and without instrumenting the code. The profiling data is printed as a sorted list of execution time per sub-program:
function samples ratio(%)
start 36144 100.00
_start 36144 100.00
main 36134 99.97
Proc_1 10476 28.98
Func_2 9885 27.34
strcmp 8161 22.57
Proc_8 2641 7.30
.div 2097 5.80
Proc_6 1412 3.90
Proc_3 1321 3.65
Proc_2 1187 3.28
.umul 1092 3.02
Func_1 777 2.14
Code coverage monitoring
The TSIM code coverage support will monitor all emulated processor memory (PROM and RAM), and register whether a memory location has been read, written or excuted. The coverage information can be displayed on the TSIM console or dumped to a file for batch processing. When the coverage is enabled, the simulation performance is decreased with approximately 30%. No impact on performance is seen when the coverage is disabled.
tsim> cov en
coverage enabled:
0x00000000 - 0x00200000 : rom
0x02000000 - 0x02400000 : ram
tsim> go
resuming at 0x02000000
Starting
Perm Towers Queens Intmm Mm Puzzle Quick Bubble Tree FFT
TSIM is highly optimised for speed and provides simulation performance of more than 1 MIPS / 100 MHz (host cpu frequency). On a high-end PC running Linux, real-time operation of a 25 MHz, 0-ws ERC32 system can readily be achieved. TSIM can also accelerate simulation time when the emulated application is in idle mode. A typical real-time application rarely loads the processor with more than 35%, allowing simulation speeds exceeding 4x real time. A collection of performance meassures are automatically calculated and can be displayed with the 'perf' command:
The following table shows the performance of TSIM-ERC32 on certain platforms in terms of raw MIPS and in relation to real ERC32 hardware running at 14 MHz (100% cpu load).
TSIM Professional (0.5% acc.)
Dhrystone CPI 1.5
GTB CPI 2.6, 15% float
Platform
Raw MIPS
Rel. perf.
Raw MOPS
Rel. perf.
Real ERC32 hardware, 14 MHz
9.3 MIPS
100%
6.8 MOPS
100%
3.0 GHz Intel Core2 (E8400), 6 Mb cache
42 MIPS
450%
40 MOPS
580%
2.2 GHz AMD64 (3400+), 1 Mb cache
25 MIPS
260%
20 MOPS
300%
3.0 GHz Xeon, 0.5 Mbyte cache
22 MIPS
230%
10 MOPS
190%
2.8 GHz P4, 0.5 Mbyte cache
20 MIPS
200%
9.5 MOPS
175%
1.6 GHz Centrino, 1 Mbyte cache
17 MIPS
175%
12 MOPS
225%
A further 10 - 30% performance improvement can be offered by reducing the timing accuracy of the simulator from 0.5% to ~ 20% (see table below). Customers interested in such a TSIM configuration can contact us for further information.
TSIM Professional (20% acc.)
Dhrystone CPI 1.5
GTB CPI 2.6, 15% float
Platform
Raw MIPS
Rel. perf.
Raw MOPS
Rel. perf.
3.0 GHz Xeon, 0.5 Mbyte cache
24 MIPS
250%
11 MOPS
220%
1.6 GHz Centrino, 1 Mbyte cache
19 MIPS
195%
14 MOPS
260%
Host support
TSIM is available for Sun Solaris (SPARC), Linux (32-bit), Linux-x64 (64-bit) and Windows 2000/XP.
Users and projects
As of writing December 2008), more than 250 commercial TSIM licenses have been sold and are being used in various LEON and ERC32 projects. Many more copies of the free evaluation version of TSIM are used by individuals and universities. TSIM is the market leader for ERC32 and LEON simulation, and used in major space projects such as Cryosat, ATV, Beagle-2, Ariane-5, GOCE, Herschel/Planck, PROBA-2 and many others.
Evaluation version
An evaluation version of TSIM/LEON3 is available from the download page.
Download
To download TSIM or the user's manual, please proceed to the download page. For pricing and availability proceed to the ordering page of TSIM.
